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PDF STD50NH02L Data sheet ( Hoja de datos )
| Número de pieza | STD50NH02L | |
| Descripción | Power MOSFET ( Transistor ) | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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STD50NH02L
N-CHANNEL 24V - 0.0085 Ω - 50A DPAK/IPAK
STripFET™ III POWER MOSFET
TYPE
VDSS
RDS(on)
ID
STD50NH02L
24 V < 0.0105 Ω 50 A
s TYPICAL RDS(on) = 0.0085 Ω @ 10 V
s TYPICAL RDS(on) = 0.012 Ω @ 5 V
s RDS(ON) * Qg INDUSTRY’s BENCHMARK
s CONDUCTION LOSSES REDUCED
s SWITCHING LOSSES REDUCED
s LOW THRESHOLD DEVICE
s THROUGH-HOLE IPAK (TO-251) POWER
PACKAGE IN TUBE (SUFFIX “-1")
s SURFACE-MOUNTING DPAK (TO-252)
POWER PACKAGE IN TAPE & REEL
(SUFFIX “T4")
DESCRIPTION
The STD50NH02L utilizes the latest advanced design
rules of ST’s proprietary STripFET™ technology. This is
suitable fot the most demanding DC-DC converter
application where high efficiency is to be achieved.
APPLICATIONS
s SPECIFICALLY DESIGNED AND OPTIMISED
FOR HIGH EFFICIENCY DC/DC CONVERTES
3
2
1
IPAK
TO-251
(Suffix “-1”)
3
1
DPAK
TO-252
(Suffix “T4”)
INTERNAL SCHEMATIC DIAGRAM
Ordering Information
SALES TYPE
STD50NH02LT4
STD50NH02L-1
MARKING
D50NH02L
D50NH02L
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Vspike(1) Drain-source Voltage Rating
VDS Drain-source Voltage (VGS = 0)
VDGR
Drain-gate Voltage (RGS = 20 kΩ)
VGS Gate- source Voltage
ID Drain Current (continuous) at TC = 25°C
ID Drain Current (continuous) at TC = 100°C
IDM(2)
Drain Current (pulsed)
Ptot Total Dissipation at TC = 25°C
Derating Factor
EAS (3) Single Pulse Avalanche Energy
Tstg Storage Temperature
Tj Max. Operating Junction Temperature
September 2003
PACKAGE
TO-252
TO-251
Value
30
24
24
± 20
50
36
200
60
0.4
280
-55 to 175
PACKAGING
TAPE & REEL
TUBE
Unit
V
V
V
V
A
A
A
W
W/°C
mJ
°C
1/12
1 page  
STD50NH02L
Normalized Gate Threshold Voltage vs Temperature
Normalized on Resistance vs Temperature
Source-drain Diode Forward Characteristics
Normalized Breakdown Voltage vs Temperature
..
5/12
5 Page 
STD50NH02L
Pconduction
Pswitching
High Side Switch (SW1)
R DS(on)SW1 * I2L * d
Low Side Switch (SW2)
R DS(on)SW2 * I2L * (1 − d )
Vin
* (Qgsth(SW1)
+ Q gd(SW1) ) * f
*
IL
Ig
Zero Voltage Switching
Pdiode Recovery
Conduction
Pgate(QG )
PQoss
Not Applicable
Not Applicable
Qg(SW1) * Vgg * f
Vin * Qoss(SW1) * f
2
1 Vin * Qrr(SW2) * f
Vf(SW2) * I L * t deadtime * f
Q gls(SW2) * Vgg * f
Vin * Qoss(SW2) * f
2
Parameter
d
Qgsth
Qgls
Pconduction
Pswitching
Pdiode
Pgate
PQoss
Meaning
Duty-cycle
Post threshold gate charge
Third quadrant gate charge
On state losses
On-off transition losses
Conduction and reverse recovery diode losses
Gate drive losses
Output capacitance losses
1 Dissipated by SW1 during turn-on
11/12
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet STD50NH02L.PDF ] | |
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