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UM6522 데이터시트 PDF




UMC에서 제조한 전자 부품 UM6522은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 UM6522 기능
기능 VERSATILE INTERFACE ADAPTER
제조업체 UMC
로고 UMC 로고


UM6522 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




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UM6522 데이터시트, 핀배열, 회로
UM6522/ UM6522A
Versatile Interface Adapter(VIA)
Features
• Two 8-bit bidirectional I/O ports
• Two 16-bit programmable timer/counters
• Serial data port
• Single +5V power supply
• TTL compatible expect Port A
• CMOS compatible peripheral Port A lines
• Expanded "handshake" capability allows positive
control of data transfers between processor and periph-
eral devices
• Latched output and input registers
• 1 MHz and 2 MHz operation
General Description
The UM6522 Versatile Interface Adapter (VIA) is a very
flexible I/O control device. In addition, this device con-
tains a pair of very powerful 16-bit interval timers, a serial-
to-parallel/parallel-to-serial shift register and input data
latching on the peripheral ports. Expanded handshaking
capability allows control of bi-directional data transfers
between VIA's in multiple processor systems.
Control of peripheral devices is handled primarily through
two 8-bit bi-directional ports. Each line can be program-
med as either an input or an output. Serveral peripheral
I/O lines can be controlled directly from the interval timers
for generating programmable frequency square waves or
for counting externally generated pulses. To facilitate
control of the many powerful features of this chip, an
interrupt flag register, an interrupt enable register and a
pair of function control registers are provided.
Pin· Configuration
VSS
PAO
PAl
PA2
PA3
PA4
PA5
PA6
PA7
PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7
CBl
CB2
VCC
Block Diagram
CAl
CA2
RSO
RSl
RS2
RS3
RES
00
01
02
03
04
05
06
07
<1>2
CSl
CS2
R/Iii
IRQ
DATA
BUS
AS3
1----+-+---- CB1
1 - - - - * - - - _ ce2
PORTB
7':"'63




UM6522 pdf, 반도체, 판매, 대치품
(f)UMC
Peripheral Interface Characteristics
Symbol,
t r, tf
TCA2
TRS
T RS2
T WHS
TDS
T RS3
T RS4
T21
TIL
TSR1
TSR2
T SR 3
TIPW
Tlcw
TIPs
TIcS
TAl
TpDH
Tpwi
TOPR
TOPL
Characteristic
Rise and Fall Time for CA 1, CB 1, CA2, and CB2
Input Signals
Delay Time, Clock Negative Transition to CA2
Negative Transition tread handshake or pulse mode)
Delay Time, Clock Negative Transition to CA2 Positive
Transition (pulse mode)
Delay Time, CA 1 Active Transition to CA2 Positive
Transition (handshake mode)
Delay Time, Clock Positive Transition to CA2 or CB2
Negative Transition (write handshake)
Delay Time, Peripheral Data Valid to CB2 Negative
Transition
Delay Time, Clock Transition to CA2 or CB2
Positive Transition (pulse mode)
Delay Time, CA 1 or CBl Active Transition to CA2 or
CB2 Positive Transition (handshake mode)
Delay Time Required from CA2 Output to CA 1
Active Transition (handshake mode)
Set-up Time, Peripheral Data Valid to CA 1 or CB 1
Active Transition (input latching)
Shift-Out Delay Time - Time from 1/>2 Falling Edge
to CB2 Data Out
Shift-In Setup Time - Time from CB2 Data in to 1/>2
Rising Edge
External Shift Clock (CB1) Setup Time Relative to
1/>2. Trailing Edge
Pulse Width - PB6 Input Pulse
Pulse Width - CBl Input Clock
Pulse Spacing - PB6 Input Pulse
Pulse Spacing - CBl Input Pulse
CAl, CBl Set Up Prior to Transition to Arrn Latch
Peripheral Data Hold After CAl, CBl Transition
Set Up Requ ired on CA 1, CB 1, CA2 or CB2 Prior to
Triggering Edge
Shift Register Clock - Delay from 1/>2
to CBl Rising Edge
to CBl Falling Edge
UM6522/ UM6522A
Min.
-
-
-
-
0.05
0.20
-
-
400
Max.
1.0
Typ.
Units
J.l.s
Figure
-
1,0 J.l.s 5a, 5b
1.0 J.l.s 5a
2,0 J.l.s 5b
1.0 J.l.S 5c, 5d
1.5 J.l.S 5c, 5d
1.0 J.l.S 5c
2.0 J.l.S 5d
- ns 5d
300 -
- 300
300 -
ns 5e
ns 5f
ns 5g
100
2 x TCY
2 x Tcy
2 x Tcy
2 x TCY
Tc + 50
150
TC + 50
TCY
-
-
-
-
-
-
-
ns 59
5i
5h
5i
5h
ns 5h
ns 5e
ns 5j
200 ns
125 ns
5k
5k
REAO IRA
- - - -OPERATION
CA2
"DATA TAKEN"
Figure 5a. CA2 Timing for Read Handshake, Pulse Mode
7-66

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UM6522 전자부품, 판매, 대치품
(DUMC
Pin Description
RES (Reset)
The reset input clears all internal registers to logic 0 (except
T1 and T2 latches and counters and the Shift Register).
This places all peripheral interface lines in the input state,
disables the timers, shift register, etc. and discables inter-
rupting from the chip.
'1>2 (Input Clock)
The input clock is the system 'I> 2 clock and is used to
tr'igger all data transfers between the system processor and
the UM6522.
R/W (Read/Write)
The direction of the data transfers between the UM6522
and the system processor is controlled by the RNV line. If
RfiiJ is low, data will be transferred out of the processor
into the selected UM6522 register (write operation). If
R/W is high and the chip is selected, data will be transferred
out of the UM6522 (read operation).
DBO-DB7 (Data Bus)
The eight bi-directional data bus lines are used to transfer
data between the UM6522 and the system processor.
During read cycles, the contents of the selected UM6522
UM6522/ UM6522A
register are placed on the data bus lines and transferred
into the processor. During write cycles, these lines
are high-impedance inputs and data is transferred from
the processor into the selected register. When the
UM6522 is unselected, the data bus lines are high-
impedance.
CS1, CS2 (Chip Selects)
The two chip select inputs are normally connected to
processor address lines either directly or through decoding.
The selected UM6522 register will be accessed when CS1
is high and CS2 is low.
RSO- RS3 (Register Selects)
The four Register Select inputs permit the system processor
to select one of the 16 internal registers of the UM6522,
as shown in Figure 6.
IRQ (Interrupt Request)
The Interrupt Request output goes low whenever an
internal interrupt flag is set and the corr84>ponding interrupt
enable bit is a logic 1. This output is "open-drain" to allow
the interrupt request signal to be "wir~-or'ed" with other
equivalent signals in the system.
Register
Number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
RS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
RS Coding
RS2 RS1
RSO
Register
Desig~
Write
Descriptions
Read
0
0
0
ORB/IRB
Output Register "B"
Input Register "B"
0
0
1
ORA/IRA
Output Register "A"
Input Register "A"
0 1 0 DDRB Data Direction Register "B"
0
1 1 DDRA
Data Direction Register "A"
1 0 0 T1C-L T1 Low-Order Latches T1 Low-Order Counter
1 0 1 T1C·H T1 High-Order Counter
1
1 0 T1 L- L
T1 Low-Order Latches
1 1 1 T1 L·H T1 High-Order Latches
0 0 0 T2C-L T2 Low-Order Latches T2 Low-Order Counter
0 0 1 T2C-H T2 High-Order Counter
0 1 0 SR
Shift Register
0 1 1 ACR
Auxiliary Control Register
1 0 0 peR
Peripheral Control Register
1 0 1 IFR
rnterru pt Flag Reg ister
1 1 0 IER
I nterrupt Enable Register
1
1
1
ORA/IRA
Same as Reg 1 Except No. "Handshake"·
Figure 6. UM6522 Internal Register Summary
7-69

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