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PDF UCN5881 Data sheet ( Hoja de datos )
| Número de pieza | UCN5881 | |
| Descripción | BiMOS II DUAL 8-BIT LATCHED DRIVER WITH READ BACK | |
| Fabricantes | Allegro | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de UCN5881 (archivo pdf) en la parte inferior de esta página. Total 4 Páginas | ||
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5881
BiMOS II DUAL
58818-BIT LATCHED DRIVER
BiMOS II DUAL 8-BIT LATCHED
DRIVER WITH READ BACK
With 16 CMOS data latches (two sets of eight), CMOS control
D PRODEUOCNTLYDwg.No.A-14,225
NTINEUFEERENCABSOLUTE MAXIMUM RATINGS
O ROutput Voltage, VOUT . . . . . . . . . . . . . . 20 V
Output Sustaining Voltage, VCE(sus) . . . 15 V
COutput Current, IOUT . . . . . . . . . . . . 50 mA
S RInput Voltage Range,
IVIN . . . . . . . . . . . -0.3 V to VDD + 0.3 V
OLogic Supply Voltage, VDD . . . . . . . . . . 15 V
D FPackage Power Dissipation,
circuitry for each set of latches, and a bipolar saturated driver for each
latch, the UCN5881EP provides low-power interface with maximum
flexibility. The driver includes thermal shutdown circuitry to protect
against damage from high junction temperatures and clamp diodes
for inductive load transient suppression.
The CMOS inputs cause minimal circuit loading and are compat-
ible with standard CMOS, PMOS, and NMOS circuits. TTL or DTL
circuits may require the use of appropriate pull up resistors. When
reading back, each data input will sink 8 mA (if its corresponding latch
is low) or source 400 µA (if its corresponding latch is high). The read
back feature is for error checking. It allows the system to verify that
data has been received and latched.
The bipolar outputs are suitable for use with low-power relays,
solenoids, and stepping motors. The very-low output saturation
voltage makes this device well-suited for driving LED arrays. The
output transistors are capable of sinking 50 mA and will maintain at
least 20 V in the OFF state. Outputs may be paralleled for higher
current capability.
The UCN5881EP dual 8-bit latched sink driver is rated for opera-
tion over the temperature range of -20°C to +85°C and is supplied in a
plastic 44-lead chip carrier conforming to the JEDEC MS-007AB
outline.
FEATURES
s 4.4 MHz Minimum Data-Input Rate
s Low-Power CMOS Logic
s 20 V, 50 mA (Max.) Outputs
s Transient-Protected Outputs
s Thermal Shutdown Protection
s Low-Profile Leaded Chip Carrier
—PD . . . . . . . . . . . . . . . . . . . See Graph
Operating Temperature Range,
TA . . . . . . . . . . . . . . . . -20°C to +85°C
Storage Temperature Range,
TS . . . . . . . . . . . . . . . -55°C to +150°C
Caution: CMOS devices have input static
protection, but are susceptible to damage when
exposed to extremely high static electrical
charges.
Always order by complete part number: UCN5881EP .
1 page | ||
| Páginas | Total 4 Páginas | |
| PDF Descargar | [ Datasheet UCN5881.PDF ] | |
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