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PDF UCN5833 Data sheet ( Hoja de datos )
| Número de pieza | UCN5833 | |
| Descripción | BiMOS II 32-BIT SERIAL-INPUT / LATCHED DRIVER | |
| Fabricantes | Allegro | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de UCN5833 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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5833
UCN5833EP
OUT 2
OUT 3
7
8
OUT 4 9
OUT 5 10
OUT 6 11
OUT 7 12
OUT 8 13
OUT 9 14
OUT10 15
OUT11 16
OUT 12 17
39 OUT31
38 OUT30
37 OUT29
36 OUT28
35 OUT27
34 OUT26
33 OUT25
32 OUT24
31 OUT23
30 OUT22
29 OUT21
SUB
Dwg. No. A-13,049
ABSOLUTE MAXIMUM RATINGS
at +25°C Free-Air Temperature
Output Voltage, VOUT . . . . . . . . . . . 30 V
Logic Supply Voltage, VDD . . . . . . . 7.0 V
Input Voltage Range,
VIN . . . . . . . . . -0.3 V to VDD + 0.3 V
Continuous Output Current,
lOUT (each output) . . . . . . . . . . 125 mA
Package Power Dissipation, PD
(UCN5833A) . . . . . . . . . . . . . . . 3.5 W*
(UCN5833EP) . . . . . . . . . . . . . . 2.5 W*
Operating Temperature Range,
TA . . . . . . . . . . . . . . -20°C to +85°C
Storage Temperature Range,
TS . . . . . . . . . . . . . -55°C to +150°C
* Derate linearly to 0 W at +150°C.
Caution: CMOS devices have input static protection
but are susceptible to damage when exposed to
extremely high static electrical charges.
BiMOS II 32-BIT SERIAL-INPUT,
LATCHED DRIVER
Designed to reduce logic supply current, chip size, and system
cost, the UCN5833A/EP integrated circuits offer high-speed operation
for thermal printers. These devices can also be used to drive multi-
plexed LED displays or incandescent lamps within their 125 mA peak
output current rating. The combination of bipolar and MOS technolo-
gies gives BiMOS II smart power ICs an interface flexibility beyond the
reach of standard buffers and power driver circuits.
These 32-bit drivers have bipolar open-collector npn Darlington
outputs, a CMOS data latch for each of the drivers, a 32-bit CMOS
shift register, and CMOS control circuitry. The high-speed CMOS shift
registers and latches allow operation with most microprocessor-based
systems at data input rates above 3.3 MHz. Use of these drivers with
TTL may require input pull-up resistors to ensure an input logic high.
The UCN5833A is supplied in a 40-pin dual in-line plastic package
with 0.600" (15.24 mm) row spacing. At an ambient temperature of
+75°C, all outputs of the DlP-packaged device will sustain 50 mA
continuously. For high-density applications, the UCN5833EP is
available. This 44-lead plastic chip carrier (quad pack) is intended
for surface-mounting on solder lands with 0.050" (1.27 mm) centers.
CMOS serial data outputs permit cascading for applications requiring
additional drive lines.
FEATURES
I To 3.3 MHz Data Input Rate
I 30 V Minimum Output Breakdown
I Darlington Current-Sink Outputs
I Low-Power CMOS Logic and Latches
Always order by complete part number:
Part Number Package
UCN5833A
40-Pin DIP
UCN5833EP
44-Lead PLCC
1 page  
40
0.580
0.485
UCN5833A
Dimensions in Inches
(controlling dimensions)
21
5833
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVER
0.015
0.008
0.700
MAX
0.600
BSC
0.250
MAX
12
0.070
0.030
3
4
2.095
1.980
20
0.100
BSC
0.005
MIN
0.015
MIN
0.022
0.014
0.200
0.115
Dimensions in Millimeters
(for reference only)
40 21
Dwg. MA-003-40 in
0.381
0.204
14.73
12.32
17.78
MAX
15.24
BSC
6.35
MAX
12 34
1.77
0.77 53.2
50.3
20
2.54
BSC
0.13
MIN
0.39
MIN
5.08
2.93
0.558
0.356
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Lead thickness is measured at seating plane or below.
Dwg. MA-003-40 mm
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet UCN5833.PDF ] | |
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