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UCQ5832EP 데이터시트 PDF




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부품번호 UCQ5832EP 기능
기능 BiMOS II 32-BIT SERIAL-INPUT / LATCHED DRIVERS
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UCQ5832EP 데이터시트, 핀배열, 회로
5832
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVERS
UCN5832A
LOGIC
SUPPLY
1 VDD
SERIAL
DATA IN
2
GROUND 3
STROBE 4
OUT 1 5
OUT2
OUT 3
OUT4
6
7
8
OUT5
OUT 6
9
10
OUT 7
OUT 8
11
12
OUT 9 12
OUT 10 14
OUT 11 15
OUT 12 16
OUT 13 17
OUT 14 18
OUT 15 19
OUT 16 20
40 CLOCK
39
SERIAL
DATA OUT
38 OUTPUT
ENABLE
37 OUT 32
36 OUT 31
35 OUT 30
34 OUT 29
33 OUT 28
32 OUT 27
31 OUT 26
30 OUT 25
29 OUT 24
28 OUT 23
27 OUT 22
26 OUT 21
25 OUT 20
24 OUT 19
23 OUT 18
22 OUT 17
21 INTERNAL
CONNECTION
Dwg. No. A-12,377A
ABSOLUTE MAXIMUM RATINGS
at +25°C Free-Air Temperature
Output Voltage, VOUT ...................... 40 V
Logic Supply Voltage, VDD ................ 15 V
Input Voltage Range,
VIN ................... -0.3 V to VDD + 0.3 V
Continuous Output Current,
lOUT .................................. 150 mA
Package Power Dissipation,
PD ................................ See Graph
Operating Temperature Range,
TA ........................... -20°C to +85°C
Storage Temperature Range,
TS .......................... -55°C to +150°C
Caution: CMOS devices have input-static
protection but are susceptible to damage when
exposed to extremely high static electrical charges.
5832
BiMOS II 32-BIT SERIAL-INPUT,
LATCHED DRIVERS
Intended originally to drive thermal printheads, the UCN5832A
and UCN5832EP have been optimized for low output-saturation
voltage, high-speed operation, and pin configurations most convenient
for the tight space requirements of high-resolution printheads. These
integrated circuits can also be used to drive multiplexed LED displays
or incandescent lamps at up to 150 mA peak current. The combination
of bipolar and MOS technologies gives BiMOS II arrays an interface
flexibility beyond the reach of standard buffers and power driver
circuits.
The devices each have 32 bipolar NPN open-collector saturated
drivers, a CMOS data latch for each of the drivers, two 16-bit CMOS
shift registers, and CMOS control circuitry. The high-speed CMOS
shift registers and latches allow operation with most microprocessor
based systems. Use of these drivers with TTL may require input
pull-up resistors to ensure an input logic high. MOS serial data
outputs permit cascading for interface applications requiring additional
drive lines.
The UCN5832A is supplied in a 40-pin dual in-line plastic package
with 0.600" (15.24 mm) row spacing. Under normal operating condi-
tions, this device will allow all outputs to sustain 100 mA continuously
without derating. The UCN5832EP is supplied in a 44-lead plastic
leaded chip carrier for minimum area, surface-mount applications.
Both devices are also available for operation from -40°C to +85°C.
To order, change the prefix from ‘UCN’ to ‘UCQ’.
Similar 32-bit serial-input latched source drivers are available as
the UCN5818AF/EPF. Other high-voltage, high-current 8-bit devices
are available as the UCN5821A, UCN5841A/LW, and UCN5842A.
FEATURES
s To 3.3 MHz Data Input Rate
s Low-Power CMOS Logic and Latches
s 40 V Current Sink Outputs
s Low Saturation Voltage
s Automotive Capable
Always order by complete part number:
Part Number
Package
UCN5832A
40-Pin DIP
UCN5832EP
44-Lead PLCC




UCQ5832EP pdf, 반도체, 판매, 대치품
5832
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVERS
CLOCK
DATA IN
STROBE
AD
B
E
C
F
OUTPUT
ENABLE
OUTN
G
Dwg. No. A-12,276A
TIMING CONDITIONS
(VDD = 5.0 V, Logic Levels are VDD and Ground)
A. Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) .......................................................................... 75 ns
B. Minimum Data Active Time After Clock Pulse
(Data Hold Time) ............................................................................. 75 ns
C. Minimum Data Pulse Width ................................................................ 150 ns
D. Minimum Clock Pulse Width ............................................................... 150 ns
E. Minimum Time Between Clock Activation and Strobe ....................... 300 ns
F. Minimum Strobe Pulse Width ............................................................. 100 ns
G. Typical Time Between Strobe Activation and
Output Transition ........................................................................... 500 ns
Serial Data present at the input is trans-
ferred to the shift register on the logic “0” to
logic “1” transition of the CLOCK input pulse.
On succeeding CLOCK pulses, the registers
shift data information towards the SERIAL
DATA OUTPUT. The SERIAL DATA must
appear at the input prior to the rising edge of
the CLOCK input waveform.
Information present at any register is
transferred to its respective latch when the
STROBE is high (serial-to-parallel conver-
sion). The latches will continue to accept
new data as long as the STROBE is held
high. Applications where the latches are
bypassed (STROBE tied high) will require
that the OUTPUT ENABLE input be low
during serial data entry.
When the OUTPUT ENABLE input is low,
all of the output buffers are disabled (OFF)
without affecting the information stored in the
latches or shift register. With the OUTPUT
ENABLE input high, the outputs are con-
trolled by the state of the latches.
TRUTH TABLE
Serial
Shift Register Contents
Data Clock
Input Input I1 I2 I3 ... IN-1 IN
Serial
Data Strobe
Output Input
Latch Contents
I1 I2 I3 ... IN-1 IN
H
H R1 R2 ... RN-2 RN-1
RN-1
L
L R1 R2 ... RN-2 RN-1
RN-1
X
R1 R2 R3 ... RN-1 RN
RN
X X X ... X X
X
L R1 R2 R3 ... RN-1 RN
P1 P2 P3 ... PN-1 PN
PN
H P1 P2 P3 ... PN-1 PN
X X X ... X X
Output
Enable
Input
H
L
Output Contents
I1 I2 I3 ... IN-1 IN
P1 P2 P3 ... PN-1 PN
H H H ... H H
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000

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UCQ5832EP 전자부품, 판매, 대치품
5832
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVERS

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부품번호상세설명 및 기능제조사
UCQ5832EP

BiMOS II 32-BIT SERIAL-INPUT / LATCHED DRIVERS

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