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ST24C01 데이터시트 PDF




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부품번호 ST24C01 기능
기능 SERIAL 1K 128 x 8 EEPROM
제조업체 ST Microelectronics
로고 ST Microelectronics 로고


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ST24C01 데이터시트, 핀배열, 회로
ST24/25C01, ST24C01R
ST24/25W01
SERIAL 1K (128 x 8) EEPROM
1 MILLION ERASE/WRITE CYCLES with
40 YEARS DATA RETENTION
SINGLE SUPPLY VOLTAGE:
– 3V to 5.5V for ST24x01 versions
– 2.5V to 5.5V for ST25x01 versions
– 1.8V to 5.5V for ST24C01R version only
HARDWARE WRITE CONTROL VERSIONS:
ST24W01 and ST25W01
TWO WIRE SERIAL INTERFACE, FULLY I2C
BUS COMPATIBLE
BYTE and MULTIBYTE WRITE (up to 4
BYTES)
PAGE WRITE (up to 8 BYTES)
BYTE, RANDOM and SEQUENTIAL READ
MODES
SELF TIMED PROGRAMMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH UP
PERFORMANCES
ST24C/W01 are replaced by the M24C01
ST25C/W01 are replaced by the M24C01-W
ST24C01R is replaced by the M24C01-R
DESCRIPTION
This specification covers a range of 1K bits I2C bus
EEPROM products, the ST24/25C01, the
ST24C01R and the ST24/25W01. In the text, prod-
ucts are referred to as ST24/25x01, where "x" is:
"C" for Standard version and "W" for hardware
Write Control version.
Table 1. Signal Names
E0-E2
SDA
SCL
Chip Enable Inputs
Serial Data Address Input/Output
Serial Clock
MODE
WC
Multibyte/Page Write Mode
(C version)
Write Control (W version)
VCC Supply Voltage
VSS Ground
NOT FOR NEW DESIGN
8
1
PSDIP8 (B)
0.25mm Frame
8
1
SO8 (M)
150mil Width
Figure 1. Logic Diagram
VCC
3
E0-E2
SCL
MODE/WC*
ST24x01
ST25x01
ST24C01R
SDA
VSS
AI00839D
Note: WC signal is only available for ST24/25W01 products.
November 1997
This is information on a product still in production but not recommended for new design
1/16




ST24C01 pdf, 반도체, 판매, 대치품
ST24/25C01, ST24C01R, ST24/25W01
SIGNAL DESCRIPTION (cont’d)
The devices with this Write Control feature no
longer support the Multibyte Write mode of opera-
tion, however all other write modes are fully sup-
ported.
Refer to the AN404 Application Note for more de-
tailed information about Write Control feature.
DEVICE OPERATION
I2C Bus Background
The ST24/25x01 support the I2C protocol. This
protocol defines any device that sends data onto
the bus as a transmitter and any device that reads
the data as a receiver. The device that controls the
data transfer is known as the master and the other
as the slave. The master will always initiate a data
transfer and will provide the serial clock for syn-
chronisation. The ST24/25x01 are always slave
devices in all communications.
Start Condition. START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A START condition must
precede any command for data transfer. Except
during a programming cycle, the ST24/25x01 con-
tinuously monitor the SDA and SCL signals for a
START condition and will not respond unless one
is given.
Stop Condition. STOP is identified by a low to high
transition of the SDA line while the clock SCL is
stable in the high state. A STOP condition termi-
nates communication between the ST24/25x01
and the bus master. A STOP condition at the end
of a Read command, after and only after a No
Acknowledge, forces the standby state. A STOP
condition at the end of a Write command triggers
the internal EEPROM write cycle.
Acknowledge Bit (ACK). An acknowledge signal
is used to indicate a successfull data transfer. The
bus transmitter, either master or slave, will release
the SDA bus after sending 8 bits of data. During the
9th clock pulse period the receiver pulls the SDA
bus low to acknowledge the receipt of the 8 bits of
data.
Data Input. During data input the ST24/25x01
sample the SDA bus signal on the rising edge of
the clock SCL. Note that for correct device opera-
tion the SDA signal must be stable during the clock
low to high transition and the data must change
ONLY when the SCL line is low.
Memory Addressing. To start communication be-
tween the bus master and the slave ST24/25x01,
the master must initiate a START condition. Follow-
ing this, the master sends onto the SDA bus line 8
bits (MSB first) corresponding to the device select
code (7 bits) and a READ or WRITE bit.
Figure 3. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus
20
VCC
16
12
8
4
VCC = 5V
SDA
MASTER SCL
RL RL
CBUS
CBUS
0
100 200 300 400
CBUS (pF)
AI01100
4/16

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ST24C01 전자부품, 판매, 대치품
Figure 5. AC Waveforms
ST24/25C01, ST24C01R, ST24/25W01
SCL
SDA IN
tCHCL
tCLCH
tDLCL
tDXCX
tCHDX
START
CONDITION
tCLDX
SDA
SDA
INPUT CHANGE
tCHDH
tDHDL
STOP &
BUS FREE
SCL
SDA OUT
tCLQV
DATA VALID
tCLQX
DATA OUTPUT
SCL
SDA IN
tDHDL
tCHDH
STOP
CONDITION
tW
WRITE CYCLE
tCHDX
START
CONDITION
AI00795
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