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PDF LXT972 Data sheet ( Hoja de datos )
| Número de pieza | LXT972 | |
| Descripción | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet | |
| Fabricantes | Level One | |
| Logotipo |  |
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Data Sheet
LXT972
FEBRUARY 2000
Revision 1.1
3.3V Dual-Speed Fast Ethernet Transceiver
General Description
The LXT972 is an IEEE compliant Fast Ethernet PHY
Transceiver that directly supports both 100BASE-TX and
10BASE-T applications. It provides a Media Independent
Interface (MII) for easy attachment to 10/100 Media
Access Controllers (MACs).
The LXT972 supports full-duplex operation at 10 Mbps
and 100 Mbps. Its operating condition can be set using
auto-negotiation, parallel detection, or manual control.
The LXT972 is fabricated with an advanced CMOS
process and requires only a single 3.3V power supply.
Applications
• Combination 10BASE-T/100BASE-TX Network
Interface Cards (NICs)
• 10/100 PCMCIA Cards
• Cable Modems and Set-Top Boxes
LXT972 Block Diagram
Features
• 3.3V Operation.
• Low power consumption (300 mW typical).
• 10BASE-T and 100BASE-TX using a single RJ-45
connection.
• Supports auto-negotiation and parallel detection.
• MII interface with extended register capability.
• Robust baseline wander correction performance.
• Standard CSMA/CD or full-duplex operation.
• Configurable via MDIO serial port or hardware
control pins.
• Integrated, programmable LED drivers.
• 64-pin Low-profile Quad Flat Package (LQFP).
• LXT972LC - Commercial (0° to 70°C ambient).
RESET
ADDR0
MDIO
MDC
MDINT
MDDIS
TX_EN
TXD <3:0>
TX_ER
TX_CLK
LED/CFG<3:1>
COL
RX_CLK
RXD<3:0>
RXDV
CRS
RX_ER
Management /
Mode Select
Logic
Register Set
Clock
Generator
Pwr Supply
Parallel/Serial
Converter
Manchester
Encoder
10
Scrambler 100
& Encoder
Register
Set
Auto
Negotiation
OSP™
Pulse
Shaper
Collision
Detect
Clock
Generator
Media
Select
Carrier Sense
Data Valid
Error Detect
Serial-to-
Parallel
Converter
Manchester
10 Decoder
100
Decoder &
Descrambler
OSP™
Slicer
+
TP
Driver
-
TP Out
OSP™
Adaptive EQ with
Baseline Wander
Cancellation
+
100TX
-
JTAG
TP In
+
10BT
-
VCC
GND
PWRDWN
REFCLK
TxSLEW<1:0>
TPOP
TPON
TDI,
TDO,
TMS,
TCK,
TRST
TPIP
TPIN
Refer to www.level1.com for most current information.
)
1 page  
LXT972 Pin Assignments
Table 1: LQFP Numeric Pin List
Pin Symbol
Type
Reference for
Full
Description
1. REFCLK/XI Input Table 4 on page 8
2. XO
Output Table 4 on page 8
3. MDDIS
Input Table 2 on page 6
4. RESET
Input Table 4 on page 8
5. TxSLEW0
Input Table 4 on page 8
6. TxSLEW1
Input Table 4 on page 8
7. GND
– Table 5 on page 9
8. VCCIO
– Table 5 on page 9
9. N/C
– Table 4 on page 8
10. N/C
– Table 4 on page 8
11. GND
– Table 5 on page 9
12. ADDR0
Input Table 4 on page 8
13. GND
– Table 5 on page 9
14. GND
– Table 5 on page 9
15. GND
– Table 5 on page 9
16. GND
– Table 5 on page 9
17. RBIAS
Analog Table 4 on page 8
Input
18. GND
– Table 5 on page 9
19. TPOP
Output Table 3 on page 7
20. TPON
Output Table 3 on page 7
21. VCCA
– Table 5 on page 9
22. VCCA
– Table 5 on page 9
23. TPIP
Input Table 3 on page 7
24. TPIN
Input Table 3 on page 7
25. GND
– Table 5 on page 9
26. GND
– Table 5 on page 9
27. TDI
Input Table 6 on page 9
28. TDO
Output Table 6 on page 9
29. TMS
Input Table 6 on page 9
30. TCK
Input Table 6 on page 9
31. TRST
Input Table 6 on page 9
32. GND
– Table 5 on page 9
33. PAUSE
Input Table 4 on page 8
Table 1: LQFP Numeric Pin List – continued
Pin Symbol
Type
Reference for
Full
Description
34. TEST0
Input Table 4 on page 8
35. TEST1
Input Table 4 on page 8
36. LED/CFG3
I/O Table 7 on page 9
37. LED/CFG2
I/O Table 7 on page 9
38. LED/CFG1
I/O Table 7 on page 9
39. PWRDWN
Input Table 4 on page 8
40. VCCIO
– Table 5 on page 9
41. GND
– Table 5 on page 9
42. MDIO
I/O Table 2 on page 6
43. MDC
Input Table 2 on page 6
44. N/C
– Table 4 on page 8
45. RXD3
Output Table 2 on page 6
46. RXD2
Output Table 2 on page 6
47. RXD1
Output Table 2 on page 6
48. RXD0
Output Table 2 on page 6
49. RX_DV
Output Table 2 on page 6
50. GND
– Table 5 on page 9
51. VCCD
– Table 5 on page 9
52. RX_CLK
Output Table 2 on page 6
53. RX_ER
Output Table 2 on page 6
54. TX_ER
Input Table 2 on page 6
55. TX_CLK
Output Table 2 on page 6
56. TX_EN
Input Table 2 on page 6
57. TXD0
Input Table 2 on page 6
58. TXD1
Input Table 2 on page 6
59. TXD2
Input Table 2 on page 6
60. TXD3
Input Table 2 on page 6
61. GND
– Table 5 on page 9
62. COL
Output Table 2 on page 6
63. CRS
Output Table 2 on page 6
64. MDINT
Open Drain Table 2 on page 6
5
5 Page 
LXT972 Functional Description
Network Media / Protocol
Support
The LXT972 supports both 10BASE-T and 100BASE-TX
Ethernet over twisted-pair.
10/100 Network Interface
The network interface port consists of two differential
signal pairs. Refer to Table 3 for specific pin assignments.
The LXT972 output drivers generate either 100BASE-TX
or 10BASE-T. When not transmitting data, the LXT972
generates 802.3-compliant link pulses or idle code. Input
signals are decoded either as a 100BASE-TX or 10BASE-
T input, depending on the mode selected. Auto-
negotiation/parallel detection or manual control is used to
determine the speed of this interface.
Twisted-Pair Interface
The LXT972 supports either 100BASE-TX or
10BASE-T connections over 100Ω, Category 5,
Unshielded Twisted Pair (UTP) cable. When operating
at 100 Mbps, the LXT971 continuously transmits and
receives MLT3 symbols. When not transmitting data,
the LXT971 generates “IDLE” symbols.
During 10 Mbps operation, Manchester-encoded data
is exchanged. When no data is being exchanged, the
line is left in an idle state. Link pulses are transmitted
periodically to keep the link up.
Only a transformer, RJ-45 connector, load resistor,
and bypass capacitors are required to complete this
interface. On the transmit side, the LXT972 has an
active internal termination and does not require exter-
nal termination resistors. Level One's patented wave-
shaping technology shapes the outgoing signal to help
reduce the need for external EMI filters. Four slew rate
settings (refer to Table 4 on page 8) allow the designer
to match the output waveform to the magnetic charac-
teristics. On the receive side, the internal impedance is
high enough that it has no practical effect on the exter-
nal termination circuit.
Fault Detection and Reporting
The LXT972 supports one fault detection and
reporting mechanism. “Remote Fault” refers to a
MAC-to-MAC communication function that is
essentially transparent to PHY layer devices. It is
used only during Auto-Negotiation, and therefore is
applicable only to twisted-pair links. “Far-End Fault”,
on the other hand, is an optional PMA-layer function
that may be embedded within PHY devices. The
LXT972 supports only the Remote Fault Function,
explained in the paragraph that follows.
Remote Fault
Bit 4.13 in the Auto-Negotiation Advertisement
Register is reserved for Remote Fault indications. It
is typically used when re-starting the auto-negotiation
sequence to indicate to the link partner that the link is
down because the advertising device detected a fault.
When the LXT972 receives a Remote Fault indication
from its partner during auto-negotiation it:
• sets bit 5.13 in the Link Partner Base Page
Ability Register, and
• sets the Remote Fault bit 1.4 in the MII Status
Register to pass this information to the local con-
troller.
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LXT972.PDF ] | |
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