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PDF ST62T42B Data sheet ( Hoja de datos )
| Número de pieza | ST62T42B | |
| Descripción | 8-BIT OTP/EPROM MCU WITH LCD DRIVER / EEPROM AND A/D CONVERTER | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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ST62T42B/E42B
8-BIT OTP/EPROM MCU WITH LCD DRIVER,
EEPROM AND A/D CONVERTER
s 3.0 to 6.0V Supply Operating Range
s 8 MHz Maximum Clock Frequency
s -40 to +85°C Operating Temperature Range
s Run, Wait and Stop Modes
s 5 Interrupt Vectors
s Look-up Table capability in Program Memory
s Data Storage in Program Memory:
User selectable size
s Data RAM: 192 bytes
s Data EEPROM: 128 bytes
s User Programmable Options
s 18 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input
– LCD segments (8 combiport lines)
s 4 I/O lines can sink up to 20mA to drive LEDs or
TRIACs directly
s Two 8-bit Timer/Counter with 7-bit
programmable prescaler
s Digital Watchdog
s 8-bit A/D Converter with 6 analog inputs
s 8-bit Synchronous Peripheral Interface (SPI)
s LCD driver with 40 segment outputs, 4
backplane outputs and selectable multiplexing
ratio.
s On-chip Clock oscillator can be driven by Quartz
Crystal or Ceramic resonator
s One external Non-Maskable Interrupt
s ST6242-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port).
DEVICE SUMMARY
DEVICE
ST62T42B
ST62E42B
OTP
(Bytes)
7948
EPROM
(Bytes)
-
7948
I/O Pins
10 to 18
10 to 18
PQFP64
CQFP64W
(See end of Datasheet for Ordering Information)
August 1999
Rev. 2.6
1/68
1
1 page  
ST62T42B/E42B
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST62T42B and ST62E42B devices are low
cost members of the ST62xx 8-bit HCMOS family
of microcontrollers, which are targeted at low to
medium complexity applications. All ST62xx de-
vices are based on a building block approach: a
Figure 1. Block Diagram
common core is surrounded by a number of on-
chip peripherals.
The ST62E42B is the erasable EPROM version of
the ST62T42B device, which may be used to em-
ulate the ST62T42B device, as well as the respec-
tive ST6242B ROM devices.
TE ST/VPP
NMI
TEST
8-BIT
A/D CONVERTER
INTERRUPT
PROGR AM
Memory
7948 bytes
DATA ROM
USE R
SELECTABLE
DATA RAM
192 Bytes
DATA EEPROM
128 Bytes
PC
STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 3
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6
8 BIT CORE
POWER OSCILLATOR RESET
SUPP LY
VDD VSS OSCin OSCout RESET
(VPP on EPROM/OTP versions only)
PORT A
PORT B
PORT C
LCD DRIVER
PA4.. PA7/Ain
PB2..PB3/Ai n
PB4/20mA Sink
PB5/Scl/20mA Sink
PB6/Sin/20mA Sink
PB7/Sout/20mA Sink
PC0.. PC7/S33..S40
S9..S32, S41..S48
COM1..COM4
VLCD
VLCD1/3
VLCD2/3
TIMER 2
TIMER 1
DIGITAL
WATCHD OG
SPI (SERIAL
PERI PHERAL
INTE RFACE)
VA0479M
5/68
5
5 Page 
ST62T42B/E42B
MEMORY MAP (Cont’d)
1.3.5 Data Window Register (DWR)
Data Window Register (DWR)
The Data Read-Only Memory window is located
from address 0040h to address 007Fh in Data
space. It allows direct reading of 64 consecutive
bytes located anywhere in program memory, be-
tween address 0000h and 1FFFh (top memory ad-
dress depends on the specific device). All the pro-
gram memory can therefore be used to store either
instructions or read-only data. Indeed, the window
can be moved in steps of 64 bytes along the pro-
gram memory by writing the appropriate code in the
Data Window Register (DWR).
The DWR can be addressed like any RAM location
in the Data Space, it is however a write-only regis-
ter and therefore cannot be accessed using single-
bit operations. This register is used to position the
64-byte read-only data window (from address 40h
to address 7Fh of the Data space) in program
memory in 64-byte steps. The effective address of
the byte to be read as data in program memory is
obtained by concatenating the 6 least significant
bits of the register address given in the instruction
(as least significant bits) and the content of the
DWR register (as most significant bits), as illustrat-
ed in Figure 5 below. For instance, when address-
ing location 0040h of the Data Space, with 0 load-
ed in the DWR register, the physical location ad-
dressed in program memory is 00h. The DWR reg-
ister is not cleared on reset, therefore it must be
written to prior to the first access to the Data read-
only memory window area.
Address: 0C9h — Write Only
70
- - DWR5 DWR4 DWR3 DWR2 DWR1 DWR0
Bits 6, 7 = Not used.
Bit 5-0 = DWR5-DWR0: Data read-only memory
Window Register Bits. These are the Data read-
only memory Window bits that correspond to the
upper bits of the data read-only memory space.
Caution: This register is undefined on reset. Nei-
ther read nor single bit instructions may be used to
address this register.
Note: Care is required when handling the DWR
register as it is write only. For this reason, the
DWR contents should not be changed while exe-
cuting an interrupt service routine, as the service
routine cannot save and then restore the register’s
previous contents. If it is impossible to avoid writ-
ing to the DWR during the interrupt service routine,
an image of the register must be saved in a RAM
location, and each time the program writes to the
DWR, it must also write to the image register. The
image register must be written first so that, if an in-
terrupt occurs between the two instructions, the
DWR is not affected.
Figure 5. Data read-only memory Window Memory Addressing
DATA ROM
13 12 11 10 9 8 7 6 5 4 3 2 1 0 PROGRAM SPACE ADDRESS
WINDOW REGISTER 7 6 5 4 3 2 1 0
READ
CONTENTS
(DWR)
5 4 3 2 1 0 DATA SPACE ADDRESS
01
40h-7Fh
IN INSTRUCTION
Example:
DWR=28h
0 10 10 0 0
DATA SPACE ADDRESS
01 0 1100 1
59h
ROM
ADDRESS:A19h
0 10 10 0 0 0 1 10 0 1
VR01 573A
11/68
11
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| PDF Descargar | [ Datasheet ST62T42B.PDF ] | |
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