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PDF MC14569B Data sheet ( Hoja de datos )
| Número de pieza | MC14569B | |
| Descripción | Programmable Divide-By-N Dual 4-Bit Binary/BCD Down Counter | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MC14569B
Programmable Divide-By-N
Dual 4-Bit Binary/BCD
Down Counter
The MC14569B is a programmable divide−by−N dual 4−bit binary
or BCD down counter constructed with MOS P−Channel and
N−Channel enhancement mode devices (complementary MOS) in
a monolithic structure.
This device has been designed for use with the MC14568B phase
comparator/counter in frequency synthesizers, phase−locked loops,
and other frequency division applications requiring low power
dissipation and/or high noise immunity.
Features
• Speed−up Circuitry for Zero Detection
• Each 4−Bit Counter Can Divide Independently in BCD or Binary Mode
• Can be Cascaded With MC14526B for Frequency Synthesizer
Applications
• All Outputs are Buffered
• Schmitt Triggered Clock Conditioning
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• This Device is Pb−Free and is RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
−0.5 to +18.0
−0.5 to VDD + 0.5
V
V
Iin, Iout Input or Output Current
(DC or Transient) per Pin
±10 mA
PD Power Dissipation, per Package
(Note 1)
500 mW
TA Ambient Temperature Range
Tstg Storage Temperature Range
TL Lead Temperature
(8−Second Soldering)
−55 to +125
−65 to +150
260
°C
°C
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Package: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
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SOIC−16 WB
DW SUFFIX
CASE 751G
PIN ASSIGNMENT
ZERO
DETECT
CTL1
P0
P1
P2
P3
CASCADE
FEEDBACK
VSS
1
2
3
4
5
6
7
8
16 VDD
15 Q
14 P7
13 P6
12 P5
11 P4
10 CTL2
9 CLOCK
MARKING DIAGRAM
16
14569B
AWLYYWWG
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
July, 2014 − Rev. 8
1
Publication Order Number:
MC14569B/D
1 page  
MC14569B
PIN DESCRIPTIONS
INPUTS
P0, P1, P2, P3 (Pins 3, 4, 5, 6) − Preset Inputs.
Programmable inputs for the least significant counter. May
be binary or BCD depending on the control input.
P4, P5, P6, P7 (Pins 11, 12, 13, 14) − Preset Inputs.
Programmable inputs for the most significant counter. May
be binary or BCD depending on the control input.
Clock (Pin 9) − Preset data is decremented by one on each
positive transition of this signal.
OUTPUTS
Zero Detect (Pin 1) − This output is normally low and
goes high for one clock cycle when the counter has
decremented to zero.
Q (Pin 15) − Output of the last stage of the most significant
counter. This output will be inactive unless the preset input
P7 has been set high.
CONTROLS
Cascade Feedback (Pin 7) − This pin is normally set
high. When low, loading of the preset inputs (P0 through P7)
is inhibited, i.e., P0 through P7 are “don’t cares.” Refer to
Table 1 for output characteristics.
CTL1 (Pin 2) − This pin controls the counting mode of the
least significant counter. When set high, counting mode is
BCD. When set low, counting mode is binary.
CTL2 (Pin 10) − This pin controls the counting mode of
the most significant counter. When set high, counting mode
is BCD. When set low, counting mode is binary.
SUPPLY PINS
VSS (Pin 18) − Negative Supply Voltage. This pin is
usually connected to ground.
VDD (Pin 16) − Positive Supply Voltage. This pin is
connected to a positive supply voltage ranging from 3.0 V
to 18 V.
OPERATING CHARACTERISTICS
The MC14569B is a programmable divide−by−N dual
4−bit down counter. This counter may be programmed (i.e.,
preset) in BCD or binary code through inputs P0 to P7. For
each counter, the counting sequence may be chosen
independently by applying a high (for BCD count) or a low
(for binary count) to the control inputs CTL1 and CTL2.
The divide ratio N (N being the value programmed on the
preset inputs P0 to P7) is automatically loaded into the
counter as soon as the count 1 is detected. Therefore, a
division ratio of one is not possible. After N clock cycles,
one pulse appears on the Zero Detect output. (See Timing
Diagram.) The Q output is the output of the last stage of the
most significant counter (See Tables 1 through 5, Mode
Controls.)
When cascading the MC14569B to the MC14526B, the
Cascade Feedback input, Q, and Zero Detect outputs must
be respectively connected to “0”, Clock, and Load of the
following counter. If the MC14569B is used alone, Cascade
Feedback must be connected to VDD.
18
16
14
12
10
8.0
6.0
4.0
2.0
0
- 40
CL = 50 pF
VDD = 15 V
10 V
5.0 V
- 20 0
+ 20 + 40 + 60 + 80 + 100
TA, AMBIENT TEMPERATURE (°C)
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5
5 Page 
MC14569B
TYPICAL APPLICATIONS
fin C
CF
Q
MC14569B
ZERO DETECT
CF
C MC14522B Q4
OR
PE MC14526B “0”
CF
C MC14522B Q4
OR
PE MC14526B “0”
Q1/C2
MC14568B
PE
“0”
DP0 - - - - - - DP3
DP0 - - - - - - DP3
DP0 - - - - - - DP3
LSD MSD fout
Figure 3. Cascading MC14568B and MC14522B or MC14526B with MC14569B
(40 kHz)
VSS
PCin PCout
C1 G
CT1 F
“0” Q1/C2
PE
DP0 - - - - DP3
VSS
VSS
Q CF
MC14569B C
ZERO DETECT
VCO
MC14011
fout
(144 - 146 MHz)
VDD
MIXER
2k
Frequencies shown in parenthesis are given as an example
2M
CRYSTAL
OSCILLATOR
(143.5 MHz)
Figure 4. Frequency Synthesizer with MC14568B and MC14569B Using a Mixer
(Channel Spacing 10 kHz)
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11
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| PDF Descargar | [ Datasheet MC14569B.PDF ] | |
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