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Número de pieza | MC14569B | |
Descripción | Programmable Divide-By-N Dual 4-Bit Binary/BCD Down Counter | |
Fabricantes | Motorola Semiconductors | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de MC14569B (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
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SEMICONDUCTOR TECHNICAL DATA
MC14569B
Programmable Divide-By-N
Dual 4-Bit Binary/BCD
Down Counter
The MC14569B is a programmable divide–by–N dual 4–bit binary or BCD
down counter constructed with MOS P–channel and N–channel enhance-
ment mode devices (complementary MOS) in a monolithic structure.
This device has been designed for use with the MC14568B phase
comparator/counter in frequency synthesizers, phase–locked loops, and
other frequency division applications requiring low power dissipation and/or
high noise immunity.
• Speed–up Circuitry for Zero Detection
• Each 4–Bit Counter Can Divide Independently in BCD or Binary Mode
• Can be Cascaded With MC14568B, MC14522B or MC14526B for
Frequency Synthesizer Applications
• All Outputs are Buffered
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΕ Schmitt Triggered Clock Conditioning
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMAXIMUM RATINGS* (Voltages Referenced to VSS)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Value
Unit
VDD DC Supply Voltage
– 0.5 to + 18.0
V
Vin, Vout
Iin, Iout
Input or Output Voltage (DC or Transient)
Input or Output Current (DC or Transient),
per Pin
– 0.5 to VDD + 0.5
± 10
V
mA
PD Power Dissipation, per Package†
500 mW
Tstg Storage Temperature
– 65 to + 150
_C
TL Lead Temperature (8–Second Soldering)
260 _C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
BLOCK DIAGRAM
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
CTL = Low for Binary Count
CTL = High for BCD Count
P0 P1 P2 P3
345 6
CTL1 CTL2
2 10
P4 P5 P6 P7
11 12 13 14
VDD = PIN 16
VSS = PIN 8
9
CLOCK
BINARY/BCD
COUNTER #1
CLOCK
LOAD
BINARY/BCD
COUNTER #2
15
Q
CASCADE 7
FEEDBACK
REV 3
1/94
©MMOotoTrOolaR, IOncL. A199C5MOS LOGIC DATA
ZERO DETECT ENCODER
1 ZERO
DETECT
MC14569B
1
1 page Table 1. Mode Controls (Cascade Feedback = Low)
Counter Control Values
Divide Ratio
CTL1
0
0
1
1
CTL2
0
1
0
1
Zero Detect
256
160
160
100
Q
256
160
160
100
NOTE: Data Preset Inputs (P0–P7) are “Don’t Cares” while Cascade Feedback is
Low.
Table 2. Mode Controls (CTL1 = Low, CTL2 = Low, Cascade Feedback = High)
Preset Inputs
Divide Ratio
Zero
P7 P6 P5 P4 P3 P2 P1 P0 Detect
Q
Comments
00000000
00000001
00000010
00000011
00001111
00010000
00100000
01000000
01111111
10000000
10001000
11111111
27 26 25 24 23 22 21 20
128 64 32 16
8
4
2
1
256
X
2
3
15
16
32
64
127
128
136
255
256
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
128
136
255
Max Count
Illegal State
Min Count
Q Output Active
Bit Value
Counter #2
Binary
Counter #1
Binary
Counting
Sequence
X = No Output (Always Low)
MOTOROLA CMOS LOGIC DATA
MC14569B
5
5 Page OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
–A–
16 9
–B–
18
CL
–T–
SEATING
PLANE
F
NK
E
G
D 16 PL
0.25 (0.010) M T A S
M
J 16 PL
0.25 (0.010) M T B S
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
INCHES
MILLIMETERS
DIM MIN MAX MIN MAX
A 0.750 0.785 19.05 19.93
B 0.240 0.295 6.10 7.49
C ––– 0.200 ––– 5.08
D 0.015 0.020 0.39 0.50
E 0.050 BSC
1.27 BSC
F 0.055 0.065 1.40 1.65
G 0.100 BSC
2.54 BSC
H 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
L 0.300 BSC
7.62 BSC
M 0_ 15_ 0_ 15_
N 0.020 0.040 0.51 1.01
–A–
16
1
H
G
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
9
B
8
FC
S
L
–T–
SEATING
PLANE
KJ
D 16 PL
0.25 (0.010) M T A M
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
INCHES
MILLIMETERS
DIM MIN MAX MIN MAX
A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC
2.54 BSC
H 0.050 BSC
1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0_ 10_ 0_ 10 _
S 0.020 0.040 0.51 1.01
MOTOROLA CMOS LOGIC DATA
MC14569B
11
11 Page |
Páginas | Total 12 Páginas | |
PDF Descargar | [ Datasheet MC14569B.PDF ] |
Número de pieza | Descripción | Fabricantes |
MC14569B | Programmable Divide-By-N Dual 4-Bit Binary/BCD Down Counter | ON Semiconductor |
MC14569B | Programmable Divide-By-N Dual 4-Bit Binary/BCD Down Counter | Motorola Semiconductors |
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