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부품번호 MC33157 기능
기능 Half Bridge Controller and Driver for Industrial Linear Tubes
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MC33157 데이터시트, 핀배열, 회로
MC33157
Half Bridge Controller and
Driver for Industrial
Linear Tubes
The MC33157 includes the oscillator circuit and two output
channels to control a half–bridge power stage.
One of the channels is ground–referenced. The second one is
floating to provide a bootstrap operation for the high side switch.
Dedicated Driver for Industrial Linear Tubes
Main oscillator is current controlled, making it easy to set up by a
single external resistor. On top of that, such a feature is useful to
implement a dimming function by frequency shift.
Filament pre–heating time control built–in.
The strike sequence is controllable by external passive components,
the resonnant frequency being independently adjustable. This
frequency can be made different from the pre–heating and the steady
state values. A frequency sweep between two defined values makes
this IC suitable for any series resonnant topologies.
Dedicated internal comparator provides an easy lamp strike detection
implementation.
Digital RESET pin provides a fast reset of the system (less than 10µs).
Both output MOSFET are set to “OFF” state when RESET is zero.
Adjustable dead time makes the product suitable for any snubber
capacitor and size of MOSFET used as power switches.
Designed to be used with standard setting capacitors 470nF.
A voltage reference, derived from the internal bandgap, is provided
for external usage. This voltage is 100% trimmed at probe level
yielding a 2% tolerance over the temperature range.
C SWEEP
R PH C PH C OP
R OP
V DD
1 4 5 3 6 7 ICO 2 +Vref
DT adjust 8
Strike 9
Detection
10
RESET
+Vref
Iph ē
15 V
UVLO
BAND GAP
REFERENCE
PREHEAT
& STRIKE CONTROL
Iph
Ifstrike
Iop
+Vref
(+7 V)
+Vref
+Vref
Latch
ENABLE
Dead Time
CONTROL LOGIC
LEVEL
SHIFTER
Vth
Q Strike Detection
C
Clear
INHIBIT
R
R
R
HIGH SIDE
BUFFER
LOW SIDE
BUFFER
16 VHS
15 VHO
14 VOUT
13 NC
12 VLO
11 GND
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16
1
SO–16L
DW SUFFIX
CASE 751G
PIN CONNECTIONS AND
MARKING DIAGRAM
VDD 1
+Vref 2
CPH 3
RPH 4
CSWEEP 5
COP 6
ICO 7
DTA 8
16 VHS
15 VHO
14 VOUT
12 VLO
11 GND
10 RESET
9 SD
AWL = Manufacturing Code
YYWW = Date Code
(Top View)
ORDERING INFORMATION
Device
Package
Shipping
MC33157DW Plastic SO–16L 47 Units / Rail
© Semiconductor Components Industries, LLC, 1999
November, 1999 – Rev. 1
1
Publication Order Number:
MC33157/D




MC33157 pdf, 반도체, 판매, 대치품
MC33157
PIN FUNCTION DESCRIPTION
Pin Symbol
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ1 VDD
Function
Supply voltage
input
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ2 +Vref
Voltage
reference
output
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ3 CPH Preheattiming
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁcapacitor
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ4 RPH
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ5 CSWEEP
Preheat and
Strike
frequencies
adjustment
resistors
Frequency
sweep timing
capacitor
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ6 COP
Oscillator
capacitor
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ7 ICO
Steady state
operating
frequency
adjustment
current input
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ8 DTA
Dead Time
Adjust
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ9 SD Strikedetection
input
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ10 RESET
Master reset
input
Description
This pin provides the DC supply to the circuit. The voltage is internally clamped by a zener
connected to the ground. It is NOT allowed to use a DC low impedance power supply to feed this
pin, but limiting the current by an external resistor is mandatory. It is recommended to damp this pin
to ground by an electrolytic capacitor connected close to pin 1.
This pin provides a +7V voltage reference derived from the internal bandgap. The +Vref can supply
up to 25 mA and shall be decoupled to ground by a 220nF ceramic capacitor
This capacitor sets two timings: filaments preheat time (tPH) and strike sequence recycle time (tSK).
It is charged with a constant current and cares must be observed to minimize the leakage current
at this pin to get the expected timing. Typically, a 0.47 µF capacitor will give a 2 seconds
pre–heating time and a 125 ms strike sequence recycle time. (See details given by figure 9)
The RPH resistor together with RENDSWEEP and COP defines the frequency used to preheat the
filaments (fPH = f1). RENDSWEEP defines the strike frequency (fENDSWEEP = f2). During the sweep
timing, the frequency will sweep from the high pre–heating f1 to the low strike f2 values. Normally,
f1 is far from the LC resonance but f2 is close enough to generate the high voltage across the
fluorescent tube. (See details given by figure 9)
This timing define the sweep time from f1 to f2. Since the timing capacitor is charged with a low
constant current, cares must be observed to minimize the leakage current at this pin to get the
expected timing. Since this capacitor is charged through resistor RPH, the voltage rises according
to an exponential and the frequency shifts with the same law.
This pin defines the steady state operation frequency (f3 = fOP) of the controller. Since this timing
capacitor is charged with a low constant current, cares must be observed to minimize the leakage
current at this pin to get the expected frequency. Film type capacitor are recommended
(polycarbonate).
Since the circuit uses a Current Controlled Oscillator (ICO), the current forced into this pin will
control the operating frequency. The allowable current range is from 1 µA to 500 µA. The +Vref
output can be used to provide the voltage across ROP. An auxiliary voltage source can be used to
implement a dimming function.
This pin provides an access to the internal timing system to adjust the dead time between the gate
drive of the High and Low power switches connected, respectively, to pin VHO and VLO.
This pin drives a comparator, with an internal fixed reference, and acknowledges the tube strike.
When a negative going slope (across the internal reference) is detected, the system considers the
lamp has struck and the oscillator jumps from the present frequency value, which is within the
window defined by RPH and RENDSWEEP to the steady state value defined by ROP. If no negative
going slope is detected on this pin, the system will repeat the sweep and strike sequence four
times, then stops. The circuit will re–start from either a RESET, or by pulling +VDD to ground. The
input signal can be either a logic level or an analog voltage ramping up from zero to +Vref followed
by a negative going slope to zero. In any case, the positive pulse width must be 1 µs minimum. The
pcb layout must be designed to minimize the noise at this pin. (See details given by figures 8, 9, &
10)
Forcing a logic zero to this pin (HCMOS low level) will reset the circuit, initializing a frequency sweep
and lamp strike sequence. The master reset does not include the pre–heating timing. The minimum
pulse width requested is 10µs to guarantee a reset state. However, this pin has no built in filtering
and a shorter pulse may initialize a reset sequence: it is the responsibility of the designer to make
sure that no noise or parasitic pulse are developed at the RESET input. A full re–start of the
sequence, including the pre–heating time, can be initialized by pulling the +VDD pin to ground. In this
case, +VDD and RESET must be simultaneously released to a high state. When RESET is asserted
low (active) both outputs MOS are biased in the off condition. An internal 20µA pull up current forces
the pin to logic one, allowing the designer to left this pin open if the RESET function is not used. In
order to avoid any uncontrolled state of the output drivers, it is recommended to set up a 10ms low
level at pin 10. The reset is activated in less than 10 microsecond, but releasing this pin while the Vcc
supply is high (above 300V) can generate a random operation, depending upon the dv/dt coming
from the power supply.
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MC33157 전자부품, 판매, 대치품
MC33157
+Vref
8
RDTA
(external)
2K
10 V
ESD
8
I
10 V
ESD
1
I/8
Internal
Circuits
Figure 5. PIN 8 DTA
2
ROP
(external)
7
10 V
ESD
I
2K
10 V
ESD
1 kW
(internal)
+Vref
1 kW
(internal)
10 V
ESD
6
2I
COP
(external)
Figure 6. PIN ICO
ph/swp switch
2K
CSWP
(external)
5
10 V
ESD
10 V
ESD
RPH
(external)
2 10 V
ESD
RENDSWEEP
(external)
I
4
10 V
ESD 2K
+Vref
10 V
ESD
1 kW
(internal)
1 kW
(internal)
6
2I
COP
(external)
Figure 7. PIN 2, 4 & 5 Vref, RPH & CSWP
wV T 1 ms
SD max
SDHIVth
4 V typ
Internal Hysterisis
SDLOVth
3.75 V typ
The Strike Detect is acknowledged as soon as the input
voltage drops below SDLOVth. It is not necessary to pull
the input voltage to zero volt or to a negative bias
SDNEG max
Figure 8. STRIKE DETECTION
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