LXT9763 Datasheet PDF - Intel
| Part Number | LXT9763 | |
| Description | Fast Ethernet 10/100 Hex Teansceiver with Full MII | |
| Manufacturers | Intel | |
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LXT9763
Fast Ethernet 10/100 Hex Transceiver with Full MII
Datasheet
The LXT9763 is a six-port PHY Fast Ethernet Transceiver that supports IEEE 802.3 physical
layer applications at both 10 and 100 Mbps. The mixed-signal adaptive equalization and clock
recovery with proprietary Optimal Signal Processing (OSP™) architecture improves SNR 3 dB
over ideal analog filters. All six network ports provide a combination twisted-pair (TP) or
pseudo-ECL (PECL) interface for a 10/100BASE-TX or 100BASE-FX connection. The
LXT9763 supports both half- and full-duplex operation at 10 and 100 Mbps.
A fully independent Media Independent Interface (MII) for each port provides maximum
control for switch and multi-port adapter applications.
In addition to an expanded set of MDIO registers, the LXT9763 provides three discrete LED
driver outputs for each port. The LXT9763 requires only a single 3.3V power supply.
Applications
s 100BASE-T, 10/100-TX, or 100BASE-FX
Switches and multi-port NICs.
Product Features
s Six independent IEEE 802.3-compliant
10BASE-T or 100BASE-TX ports with
integrated filters.
s Proprietary Optimal Signal Processing™
(OSP™) architecture improves SNR by 3
dB over ideal analog filters.
s Baseline wander correction for improved
100BASE-TX performance.
s 100BASE-FX fiber-optic capability on all
ports.
s Supports both auto-negotiation and legacy
systems without auto-negotiation
capability.
s JTAG boundary scan.
s Six MII ports for independent PHY port
operation.
s Configurable via MDIO port or external
control pins.
s Maskable interrupts.
s Very low power 3.3V operation
(380 mW per channel, typical).
s 208-pin PQFP (0-70 oC ambient
temperature range).
As of January 15, 2001, this document replaces the Level One document
LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII.
Order Number: 249110-001
January 2001
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Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763
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LXT9763 Block Diagram ....................................................................................... 9
LXT9763 Pin Assignments ..................................................................................10
LXT9763 Interfaces ............................................................................................17
Port Address Scheme ........................................................................................19
Management Interface Read Frame Structure ...................................................19
Management Interface Write Frame Structure ...................................................20
Interrupt Logic ....................................................................................................20
Initialization Sequence .......................................................................................22
Hardware Configuration Settings .......................................................................23
Overview of Link Establishment .........................................................................25
MII Data Interface ...............................................................................................26
Loopback Paths ..................................................................................................27
100BASE-X Frame Format ................................................................................28
100BASE-TX Data Path .....................................................................................29
Protocol Sublayers .............................................................................................30
LED Pulse Stretching .........................................................................................36
Power and Ground Supply Connections ............................................................41
Typical Twisted-Pair Interface ............................................................................42
Typical Fiber Interface ........................................................................................43
100BASE-TX Receive Timing (4B Mode) ...........................................................47
100BASE-TX Transmit Timing (4B Mode) .........................................................48
100BASE-TX Receive Timing (5B Mode) ..........................................................49
100BASE-TX Transmit Timing (5B Mode) .........................................................50
100BASE-FX Receive Timing ............................................................................51
100BASE-FX Transmit Timing ...........................................................................52
10BASE-T Receive Timing .................................................................................53
10BASE-T Transmit Timing ................................................................................54
10BASE-T SQE (Heartbeat) Timing ...................................................................54
10BASE-T Jab and Unjab Timing ......................................................................55
Auto Negotiation and Fast Link Pulse Timing ....................................................55
Fast Link Pulse Timing .......................................................................................56
MDIO Write Timing (MDIO Sourced by MAC) ....................................................56
MDIO Read Timing (MDIO Sourced by PHY) ....................................................57
Power-Up Timing ................................................................................................57
RESET And Power-Down Recovery Timing ......................................................58
PHY Identifier Bit Mapping .................................................................................64
LXT9763 Package Specification .........................................................................73
Datasheet
5
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| Information | Total 30 Pages | |
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