|
|
PDF LXT9763 Data sheet ( Hoja de datos )
| Número de pieza | LXT9763 | |
| Descripción | Fast Ethernet 10/100 Hex Teansceiver with Full MII | |
| Fabricantes | Level One | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de LXT9763 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
Data Sheet
LXT9763
APRIL 2000
Revision 1.2
Fast Ethernet 10/100 Hex Transceiver with Full MII
General Description
Features
The LXT9763 is a six-port PHY Fast Ethernet Transceiver
that supports IEEE 802.3 physical layer applications at
both 10 and 100 Mbps. The mixed-signal adaptive
equalization and clock recovery with proprietary Optimal
Signal Processing (OSP™) architecture improves SNR
3 dB over ideal analog filters. All six network ports
provide a combination twisted-pair (TP) or pseudo-ECL
(PECL) interface for a 10/100BASE-TX or 100BASE-FX
connection. The LXT9763 supports both half- and full-
duplex operation at 10 and 100 Mbps.
A fully independent Media Independent Interface (MII)
for each port provides maximum control for switch and
multi-port adapter applications.
In addition to an expanded set of MDIO registers, the
LXT9763 provides three discrete LED driver outputs for
each port. The LXT9763 requires only a single 3.3V power
supply.
Applications
• 100BASE-T, 10/100-TX, or 100BASE-FX Switches
and multi-port NICs.
• Six independent IEEE 802.3-compliant 10BASE-T or
100BASE-TX ports with integrated filters.
• Proprietary Optimal Signal Processing™ (OSP™)
architecture improves SNR by 3 dB over ideal analog
filters.
• Baseline wander correction for improved 100BASE-
TX performance.
• 100BASE-FX fiber-optic capability on all ports.
• Supports both auto-negotiation and legacy systems
without auto-negotiation capability.
• JTAG boundary scan.
• Six MII ports for independent PHY port operation.
• Configurable via MDIO port or external control pins.
• Maskable interrupts.
• Very low power 3.3V operation
(380 mW per channel, typical).
• 208-pin PQFP (0-70 oC ambient temperature range).
LXT9763 Block Diagram
RESET
CFG<2:0>
ADD<4:0>
MDIO
MDC
MDINT
TX_ENn
TXDn_<3:0>
TX_ERn
TX_CLKn
LED/CFGn_<3:0>
COLn
RX_CLKn
RXDn_<3:0>
RXDVn
CRSn
RX_ERn
Management /
Mode Select
Logic
Global Functions
Clock
Generator
Pwr Supply
Register Set
Parallel/Serial
Converter
Manchester
Encoder
10
Scrambler 100
& Encoder
Register
Set
Auto
Negotiation
OSP™
Pulse
Shaper
Collision
Detect
Clock
Generator
Media
Select
Carrier Sense
Data Valid
Error Detect
Serial to
Parallel
Converter
Manchester
10 Decoder
100 Decoder &
Descrambler
OSP™
Slicer
Per-Port Functions
+
TP
Driver
-
+
ECL
Driver
-
OSP™
Adaptive EQ with
BaseLine Wander
Cancellation
+
100TX
-
+
100FX
-
+
10BT
PORT 0
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
-
TP / Fiber
Out
TP / Fiber
In
Refer to www.level1.com for most current information.
VCC
GND
REFCLK
TPFOP n
TPFON n
TPFIP n
TPFIN n
)
1 page  
LXT9763 Pin Assignments and Signal Descriptions
Table 1: LXT9763 MII Signal Descriptions
Pin#
Symbol
Type1
Signal Description2
Data Interface Pins
79 TXD0_0
82 TXD0_1
83 TXD0_2
84 TXD0_3
I Transmit Data - Port 0. 4-bit parallel data to be transmitted from port 0 is
clocked in synchronously to TX_CLK. In symbol mode (16.11 = 1), the port
transmit error signal is re-mapped to provide a fifth data bit.
60 TXD1_0
61 TXD1_1
62 TXD1_2
63 TXD1_3
I Transmit Data - Port 1. 4-bit parallel data to be transmitted from port 1 is
clocked in synchronously to TX_CLK. In symbol mode (16.11 = 1), the port
transmit error signal is re-mapped to provide a fifth data bit.
42 TXD2_0
43 TXD2_1
44 TXD2_2
45 TXD2_3
I Transmit Data - Port 2. 4-bit parallel data to be transmitted from port 2 is
clocked in synchronously to TX_CLK. In symbol mode (16.11 = 1), the port
transmit error signal is re-mapped to provide a fifth data bit.
24 TXD3_0
25 TXD3_1
26 TXD3_2
27 TXD3_3
I Transmit Data - Port 3. 4-bit parallel data to be transmitted from port 3 is
clocked in synchronously to TX_CLK. In symbol mode (16.11 = 1), the port
transmit error signal is re-mapped to provide a fifth data bit.
6 TXD4_0
7 TXD4_1
8 TXD4_2
9 TXD4_3
I Transmit Data - Port 4. 4-bit parallel data to be transmitted from port 4 is
clocked in synchronously to TX_CLK. In symbol mode (16.11 = 1), the port
transmit error signal is re-mapped to provide a fifth data bit.
196 TXD5_0
197 TXD5_1
198 TXD5_2
199 TXD5_3
I Transmit Data - Port 5. 4-bit parallel data to be transmitted from port 5 is
clocked in synchronously to TX_CLK. In symbol mode (16.11 = 1), the port
transmit error signal is re-mapped to provide a fifth data bit.
77 TX_EN0
59 TX_EN1
41 TX_EN2
23 TX_EN3
5 TX_EN4
195 TX_EN5
I Transmit Enable - Ports 0 - 5. Active High input enables respective port
transmitter. This signal must be synchronous to the TX_CLK.
75 TX_ER0/TXD0_4 I Transmit Coding Error - Ports 0 - 5. Valid during 100 Mbps operation only.
57 TX_ER1/TXD1_4
This signal must be driven synchronously to TX_CLK. When High, forces
39 TX_ER2/TXD2_4
the respective port to transmit Halt (H) code group.
21 TX_ER3/TXD3_4
3 TX_ER4/TXD4_4
191 TX_ER5/TXD5_4
Transmit Data - Ports 0 - 5. During symbol mode operation (16.11 = 1),
these signals are re-mapped to provide the fifth data bit (TXDn_4) for their
respective ports (n).
1. Type Column Coding: I = Input, O = Output, OD = Open Drain
2. The LXT9763 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation, where X is the register
number (0-32) and Y is the bit number (0-15).
5
5 Page 
LXT9763 Functional Description
FUNCTIONAL DESCRIPTION
Introduction
The LXT9763 six-port Fast Ethernet 10/100 Transceiver
supports 10 Mbps and 100 Mbps networks. It complies
with all applicable requirements of IEEE 802.3. Each port
directly drives either a 100BASE-TX line (up to 100
meters) or a 10BASE-T line (up to 185 meters). The
LXT9763 also supports 100BASE-FX operation via a
Pseudo-ECL (PECL) interface.
OSP™ Architecture
Level One's LXT9763 incorporates high-efficiency
Optimal Signal Processing™ design techniques,
combining the best properties of digital and analog signal
processing to produce a truly optimal device.
The receiver utilizes decision feedback equalization to
increase noise and cross-talk immunity by as much as 3 dB
over an ideal all-analog equalizer. Using OSP mixed-signal
processing techniques in the receive equalizer avoids the
quantization noise and calculation truncation errors found
in traditional DSP-based receivers (typically complex DSP
engines with A/D converters). This results in improved
receiver noise and cross-talk performance.
The OSP signal processing scheme also requires
substantially less computational logic than traditional DSP-
based designs. This lowers power consumption and also
reduces the logic switching noise generated by high-speed
DSP engines. This logic switching noise can be a
considerable source of EMI generated on the device’s
power supplies.
The OSP-based LXT9763 provides improved data
recovery, EMI performance, and power consumption.
Comprehensive Functionality
The LXT9763 provides six standard Media Independent
Interfaces (MIIs) for 10/100 MACs, each serving an
individual network port. The LXT9763 performs all
functions of the Physical Coding Sublayer (PCS) and
Physical Media Attachment (PMA) sublayer as defined in
the IEEE 802.3 100BASE-X specification. This device
also performs all functions of the Physical Media
Dependent (PMD) sublayer for 100BASE-TX connections.
On power-up, the LXT9763 reads its configuration pins to
check for forced operation settings. If not configured for
forced operation, each port uses auto-negotiation/parallel
detection to automatically determine line operating
conditions. If the PHY device on the other side of the link
supports auto-negotiation, the LXT9763 auto-negotiates
with it using Fast Link Pulse (FLP) bursts. If the PHY
partner does not support auto-negotiation, the LXT9763
automatically detects the presence of either link pulses (10
Mbps PHY) or Idle symbols (100 Mbps PHY) and set its
operating conditions accordingly.
The LXT9763 provides half-duplex and full-duplex
operation at 100 Mbps and 10 Mbps.
Interface Descriptions
Figure 2: LXT9763 Interfaces
MII
Data
I/F
MII
Mgmt
I/F
Hardware
Control I/F
& Port LEDs
TX_CLKn
TXDn_<3:0>
TX_ENn
TX_ERn
TPFOPn
TPFONn
RX_CLKn
RXDn_<3:0>
RX_DVn
RX_ERn
COLn
CRSn
TPFIPn
TPFINn
MDIO
MDC
MDINT
Network
I/F
ADD<4:0>
LED/CFGn_1
LED/CFGn_2
LED/CFGn_3
RBIAS
22.1k
VCCIO
VCCD
GNDD
+3.3V
+3.3V
.01uF
10/100 Network Interface
The LXT9763 supports both 10BASE-T and
100BASE-TX Ethernet over twisted-pair, or 100 Mbps
Ethernet over fiber media (100BASE-FX). Each of the six
network interface ports consists of four external pins (two
differential signal pairs). The pins are shared between
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LXT9763.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| LXT9763 | Fast Ethernet 10/100 Hex Teansceiver with Full MII |  Intel |
| LXT9763 | Fast Ethernet 10/100 Hex Teansceiver with Full MII | Level One |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |