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부품번호 TSA5520 기능
기능 (TSA5521) 1.3 GHz universal bus-controlled TV synthesizer
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TSA5520 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
DATA SHEET
TSA5520; TSA5521
1.3 GHz universal bus-controlled
TV synthesizer
Product specification
Supersedes data of 1995 Mar 16
File under Integrated Circuits, IC02
1996 Oct 10




TSA5520 pdf, 반도체, 판매, 대치품
Philips Semiconductors
1.3 GHz universal bus-controlled
TV synthesizer
Product specification
TSA5520; TSA5521
GENERAL DESCRIPTION
The device is a single-chip PLL frequency synthesizer
designed for TV and VCR tuning systems. The circuit
consists of a divide-by-eight prescaler with its own
preamplifier, a 15-bit programmable divider, a crystal
oscillator and its programmable reference divider and a
phase/frequency detector combined with a charge-pump
which drives the tuning amplifier and the 33 V output.
Four high-current PNP band switch buffers are provided
for band switching. Two PNP buffers can be switched on
simultaneously. The sum of the collector currents is limited
to 50 mA.
Depending on the reference divider ratio (512, 640 or
1024), the phase comparator operates at 3.90625 kHz,
6.25 kHz or 7.8125 kHz using a 4 MHz crystal.
The lock detector output is LOW when the PLL loop is
locked. In the test mode, this output is used as a test
output for fref and 1/2fdiv (see Table 6). The device can be
controlled in accordance with the I2C-bus format or the
3-wire bus format depending on the voltage applied to the
SW input (see Table 2).
I2C-bus format (SW = LOW)
Five serial bytes (including address byte) are required to
address the device, select the VCO frequency, program
the four PNP band switch buffers, set the charge-pump
current and the reference divider ratio.
The device has three independent I2C-bus addresses
which can be selected by applying a specific voltage on the
CE input (see Table 5). The general address C2 is always
valid. When the I2C-bus format is fully used, TSA5520 and
TSA5521 are equal.
3-wire bus format (SW = VCC1 or open-circuit)
Data is transmitted to the device during a HIGH level on
the CE input (enable line pin 15). The device is compatible
with 18-bit and 19-bit data formats. The first four bits are
used to program the PNP band switch buffers and the
remaining bits are used to control the programmable
divider. A 27-bit data format may also be used to set the
charge-pump current, the reference divider ratio and for
test purposes. The difference between TSA5520 and
TSA5521 are given in Table 1.
When the 27-bit format is used, the TSA5520 and
TSA5521 are equal and the reference divider is controlled
by the RSA and RSB bits (see Table 7). More details are
given in Chapter “Functional description” Section “3-wire
bus mode (SW = open-circuit or VCC1); see
Figs 3, 4 and 5”.
Table 1 Differences between TSA5520 and TSA5521
TYPE NUMBER
TSA5520
TSA5520
TSA5521
DATA WORD
18-bit
19-bit
18-bit or 19-bit
REFERENCE DIVIDER
512(1)
1 024(1)
640(2)
FREQUENCY STEP (kHz)
62.5
31.25
50
Notes
1. The selection of the reference divider is given by an automatic identification of the data word length.
2. The reference divider is set to 640 at power-on reset.
1996 Oct 10
4

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TSA5520 전자부품, 판매, 대치품
Philips Semiconductors
1.3 GHz universal bus-controlled
TV synthesizer
Product specification
TSA5520; TSA5521
Table 2 Bus format selection
PIN NAME
11 SW
13 SCL
14 SDA
15 CE
3-WIRE BUS MODE
open or HIGH
clock input
data input
chip enable input
I2C BUS MODE
LOW
SCL input
SDA input/output
address selection input
Table 3 I2C-bus data format
BYTE
MSB
DATA BYTE
LSB
Address Byte (ADB)
1
1
0
0
0 MA1 MA0 0
Divider Byte 1 (DB1)
0 N14 N13 N12 N11 N10 N9 N8
Divider Byte 2 (DB2) N7 N6 N5 N4 N3 N2 N1 N0
Control Byte (CB)
1 CP T2 T1 T0 RSA RSB OS
Band switch Byte (BB) X X X X BS4 BS3 BS2 BS1
SLAVE ANSWER
A
A
A
A
A
Table 4 Description of Table 3
SYMBOL
A
MA1 and MA0
N14 to N0
CP
T2 to T0
RSA and RSB
OS
BS4 to BS1
X
DESCRIPTION
acknowledge
programmable address bits (see Table 5)
programmable divider bits; N = N14 × 214 + N13 × 213 + ... + N1 × 2 + N0
charge-pump current; CP = 0 = 60 µA; CP = 1 = 280 µA
test bits (see Table 6); for normal operation T2 = 0, T1 = 0 and T0 = 1
reference divider ratio select bits (see Table 7)
tuning amplifier control bit; for normal operation OS = 0 and tuning voltage is ON;
when OS = 1 tuning voltage is OFF (high impedance)
PNP band switch buffers control bits; when BSn = 0 buffer n is OFF;
when BSn = 1 buffer n is ON
don’t care
Table 5 I2C-bus address selection
VOLTAGE APPLIED TO THE
CE INPUT (SW = LOW)
0 to 0.1VCC1
Always valid
0.4VCC1 to 0.6VCC1
0.9VCC1 to VCC1
MA1
0
0
1
1
MA0
0
1
0
1
1996 Oct 10
7

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