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PDF MC145750 Data sheet ( Hoja de datos )
| Número de pieza | MC145750 | |
| Descripción | QPSK Encoder | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Product Preview
QPSK Encoder
The MC145750 is a silicon gate HCMOS device designed to encode π/4–shift
QPSK baseband signals. The device contains two 10–bit DACs for the I/Q
signal, Root–Nyquist digital filtering, and burst rising and falling edge
processing for digital RF communication equipment. Primary applications for
this device are in products that will be used in PHS (384 kbps) and PDC
(42 kbps). It will perform up to 800 kbps data rate. It also contains PN511
random pattern generator and timing generator with PLL.
• Root–Nyquist Digital Filtering (Coefficient = 0.5)
• Burst Edge Processing Circuitry (Ramp–Up and –Down)
• Two 10–Bit DACs for I/Q Output
• Operating Voltage Range: 2.7 to 5.5 V
• PN511 Random Pattern Generator
• Conformance to RCR Standard for PHS, PDC
• Variable Data Transmission Rate up to 800 kbps (VDD = 5 V)
• Timing Generator with PLL
• QPSK Mode, Burst, and Continuous I/Q Signal Output is Performed
• Companion Device is MRFIC0001
PIN ASSIGNMENT
NC
PB1
CF
PCO
PLL
ECLK
DVDD
DVSS
DCLK
DS/STBY
TXD
ERST/PDN
36
37
48
1
25
24 TB7
TNO/TB8
BW/TB9
NC
Iout
DAref3
DAref2
DAref1
DAref
Qout
DAVSS
13 DAVDD
12
NC = NO CONNECTION
Order this document
by MC145750/D
MC145750
VFU SUFFIX
PLASTIC VQFP
CASE 932
ORDERING INFORMATION
MC145750VFU VQFP
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
REV 2
10/95
©MOMoTtoOroRla,OInLc.A1995
MC145750
1
1 page  
PIN DESCRIPTIONS
POWER SUPPLY
VSS
Digital Ground (Pins 6, 44)
These are the negative power supply input pins to the digi-
tal portion of the device and are connected to ground (0 V).
VDD
Positive Power Supply Input (Pins 7, 43)
These are the positive power supply input pins to the digi-
tal portion of the device. Typical operating voltage range is
3.3 V at DAref3 = H, 5.0 V at DAref1 = H. Power should be
fed simultaneously with DAVDD pin in order to avoid any pos-
sible damage to the device.
DAVDD
Positive Power Supply Input for DACs (Pin 13)
This is the positive power supply input pin to the analog
portion of the device. Typical operating voltage range is 2.7 V
to 5.5 V.
DAVSS
Analog Ground for DACs (Pin 14)
This is the negative power supply pin to the analog portion
of the device and is connected to ground.
MODE CONTROL AND TEST
MODE0 – MODE2
Normal/Test Mode Select (Pins 1, 2, 3)
These pins must be connected to ground for normal opera-
tion. For system test, PN pattern generation mode will be
performed when MODE0 = H and MODE1, MODE2 = L.
PN511 signal is fed to the encoder instead of input data from
TXD pin. Data shift timing is the same as the normal opera-
tion mode and burst timing indicated by DS pin is still valid for
the device. The PN511 signal is monitored at the PNO pin.
TEST
Test Mode (Pin 4)
The device operates normally while this pin is held low.
When this signal is high, the device enters into factory test
mode. Only one mode is allowed to be enacted by user for
PN Mode.
DRATE
Data–Rate Select (Pin 9)
This pin can select high data rate when it is low, such as in
PHS applications.
QPSK
(D)QPSK/π/4–Shift QPSK Mode Select (Pin 10)
The device operates as a π/4–QPSK Encoder when this
pin is held high. By making this pin low, it functions as non–
shift differential QPSK Encoder. All of the functions are the
same in both modes.
PN0/TB8
PN511 Test Pattern Output/Test Bus 8 (Pin 23)
This is the output data of PN511 test–pattern in normal
mode. When the PN pattern generator outputs to this pin, it
can be output I/Q pins and data from TXD pin may be ig-
nored. If the DS signal is L, I/Q pins stop but PN data stream
may be output.
TB0 – TB7
Test Bus (Pins 24, 26 – 32)
These pins are used in factory test and should be con-
nected to ground for normal operation.
PLL
Int/Ext PLL Clock Select (Pin 41)
When this pin is connected to ground, the PLL is active
and timing will be generated internally. When this pin is con-
nected to VDD, timing should be applied to the ECLK pin.
DIGITAL INTERFACE PINS
BW/TB9
Burst Window Output/Test Bus 9 (Pin 22)
This output indicates when modulated baseband I/Q sig-
nals are output from this device. This pin is used as the trans-
mission control signal for saving power for RF.
ECLK
External Clock Input (Pin 42)
When the internal timing generator with PLL is not used in
the system, this pin must have 15.36 MHz applied as a sys-
tem clock for this device. This pin is connected to ground for
normal operation.
DCLK
Data Shift Clock Input (Pin 45)
This is the shift clock input for the transmit data input and is
typically 384 kHz for the PHS (DRATE Pin = L) and 42 kHz
for the PDC (DRATE Pin = H) application. The data input oc-
curs at the rising edge of the DCLK. For burst–type systems
such as the TDMA data transmission applications, this signal
must be synchronized with the rising/falling edge of the DS
pin (Data Slot Timing Input).
DS/STBY
Data Slot Timing/Standby Input (Pin 46)
For burst–type, this input signal indicates when transmit
data are valid for the device. Its duration must be equal with
the number of input data to the device, and its transition must
be aligned with the rising edge of the DCLK signal.
When a logic L is applied to this pin, all digital portions ex-
cept the timing generator are not clocked and the device is in
a low power dissipation mode. When a logic H is applied con-
tinuously, all input data are encoded as valid data.
TXD
Transmit Data Input (Pin 47)
Data bit streams to be transmitted are input to this pin. The
data is valid only when the DS (Pin 46) is asserted (high). Its
transition should be synchronized with rising edge of the
DCLK (Pin 45).
MOTOROLA
MC145750
5
5 Page 
PACKAGE DIMENSIONS
VFU SUFFIX
PLASTIC VQFP
CASE 932–02
4X
0.200 (0.008) AB T–U Z
9A
A1
48
37
DETAIL Y
P
1
–T–
36
–U–
B
B1
12
V
V1
25
AE
13
S1
24
–Z–
S
4X
0.200 (0.008) AC T–U Z
–T–, –U–, –Z–
DETAIL Y
G
–AB–
–AC–
AD
ÇÇÇÇÇÇÇÇÉÉÉÉBAÇÇÇÇÉÉÉÉSEMÇÇÇÇÉÉÉÉETALN J
F
D
0.080 (0.003) M AC T–U S Z S
SECTION AE–AE
0.080 (0.003) AC
M_
TOP & BOTTOM
CE
HW
DETAIL AD
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –AB– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED
AT DATUM PLANE –AB–.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –AC–.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –AB–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
AE NOT CAUSE THE D DIMENSION TO EXCEED
0.350 (0.014).
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 7.000 BSC
0.276 BSC
A1 3.500 BSC
0.138 BSC
B 7.000 BSC
0.276 BSC
B1 3.500 BSC
0.138 BSC
C 1.400 1.600 0.055 0.063
D 0.170 0.270 0.007 0.011
E 1.350 1.450 0.053 0.057
F 0.170 0.230 0.007 0.009
G 0.500 BASIC 0.020 BASIC
H 0.050 0.150 0.002 0.006
J 0.090 0.200 0.004 0.008
K 0.500 0.700 0.020 0.028
M 12_REF
12 _REF
N 0.090 0.160 0.004 0.006
P 0.250 BASIC 0.010 BASIC
Q 1_ 5_ 1_ 5_
R 0.150 0.250 0.006 0.010
S 9.000 BSC
0.354 BSC
S1 4.500 BSC
0.177 BSC
V 9.000 BSC
0.354 BSC
V1 4.500 BSC
0.177 BSC
W 0.200 REF
0.008 REF
X 1.000 REF
0.039 REF
R
GAUGE PLANE
0.250 (0.010)
Q_
K
X
MOTOROLA
MC145750
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet MC145750.PDF ] | |
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