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부품번호 | BL8531H 기능 |
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기능 | 12 Bit 10MSPS ADC | ||
제조업체 | Samsung | ||
로고 | |||
BL8531H
AFE FOR CCD/CIS SIGNAL PROCESSOR
GENERAL DESCRIPTION
The samsung analog front end(AFE) for CCD/CIS image signal is an integrated analog signal processor for color
image signal.
The AFE converts CCD/CIS output signal to digital data. The AFE includes three-channel CDS(Correlated
Double Sampling) circuit, PGA(Programmable Gain Amplifier), and 12-bit analog to digital converter with
reference generator.
A parallel data bus provides a simple interface to 8-bit microcontroller.
APPLICATIONS
• Color and B/W Scanner
• Digital Copiers
• Facsimile
• General Purpose CCD/CIS imager
FETURES
• 12-bit 6MSPS A/D Converter
• Integrated Triple Correlated Double Sampler
• 3-Channel 2 MSPS Color Mode
• Analog Programmble Gain Amplifier
• Internal Voltage Reference
• Wide clamp level controllability for CIS sensor
• No Missing Code Guaranteed
• Microcontroller-Compatible Control Interface
• Operation by Single 5V Supply
• CMOS Low Power Dissipation
KEY SPECIFICATION
• Resolution: 12-bit
• Conversion Rate: 6 MHz(2 MHz*3)
• Supply Voltage: 5 V ± 5%
• Power Dissipation: 375 mW(Typical)
1
AFE FOR CCD/CIS SIGNAL PROCESSOR
CORE PIN CONFIGURATION
BL8531H
R_VIN
G_VIN
B_VIN
VSSA2
VDDA2
VSSA1
VDDA1
BGR REFT VCOM REFB
EXT_MCTL
MCTL1,MCTL2
VDDD
VSSD
VBB
STRTLN
bl8531h
D[11:0]/MPU[7:0]
AD[2:0]
CSB
WRB
RDB
OEB
ADCCLK
CDS1_CLK CDS2_CLK
ABSOLUTE MAXIMUM RATINGS
Charateritics
Supply Voltage
Analog Input Voltage
Digital Input Voltage
Digital Output Voltage
Reference Voltage
Storage Temperature Range
Operating Temperature Range
Symbol
VDD
AIN
CLK
VOH, VOL
VRT/VRB
Tstg
Topr
Value
6.5
VSS to VDD
VSS to VDD
VSS to VDD
VSS to VDD
-45 to 150
0 to 70
Units
V
V
V
V
V
°C
°C
NOTES:
1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently. Exposure to
ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied with
the other values kept within the following operating conditions and function operation under any of these conditions is not
implied.
2. All voltages are measured with respect to VSS unless otherwise specified.
3. 100pF capacitor is discharged through a 1.5kΩ resistor (Human body model)
4
4페이지 BL8531H
AFE FOR CCD/CIS SIGNAL PROCESSOR
TIMING SPECIFICATIONS
(VDDA = 5V, VDDD = 5V unless otherwise noted)
Characteristics
3-Channel Conversion Rate
1-Channel Conversion Rate
CDSCLK1 Pulse Width
CDSCLK2 Pulse Width
CDSCLK2B Pulse Width
CDSCLK1 Falling to CDSCLK2 Rising
CDSCLK2 Falling to CDSCLK1 Rising
ADCCLK Pulse Width
CDSCLK2 Rising to ADCCLK Rising
CDSCLK2 Falling to ADCCLK Falling
ADCCLK Rising to CDS2CLK Falling
STRTLN Rising, Falling Setup & Hold
ADC Output Delay
Register Address Setup Time
Register Address Hold Time
Data Hold Time
Register Chip Select Setup Time
Register Chip Select Hold Time
Register Read Pulse Width
Write Pulse Width
Register Read To Data Valid
Output Enable High to Tri-State
Tri-State to Data Valid
Aperture Delay
Latency for 1 Channel mode
Symbol
tC1CLK
tC2CLK
tC2CLKB
tC1C2A
tC2C1A
tADCLK
tC2ADA
tC2ADB
tADC2A
tS, tH
tADDT
tAS
tAH
tDH
tCSS
tCSH
tPWR
tPWW
tDD
tHZ
tDEV
tAD
Min Typ Max Unit
500 ns
166 ns
60 ns
70 ns
70 ns
5 ns
5 ns
70 ns
70 ns
5 ns
5 ns
15 ns
20 ns
15 ns
15 ns
15 ns
15 ns
15 ns
50 ns
25 ns
40 ns
10 ns
15 ns
2 ns
4 ADCCL
K Cycles
* Aperture delay is a timing measurement between the sampling clocks and CDS. It is measured from the falling
edge of the CDS2_CLK input to when the input signal is held for data conversion
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7페이지 | |||
구 성 | 총 30 페이지수 | ||
다운로드 | [ BL8531H.PDF 데이터시트 ] |
당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는 |
구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
BL8531 | High Efficiency Low Noise PFM Step-up DC/DC Converter | SHANGHAI BELLING |
BL8531H | 12 Bit 10MSPS ADC | Samsung |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |