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BL8531H 데이터시트 PDF




Samsung에서 제조한 전자 부품 BL8531H은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 BL8531H 자료 제공

부품번호 BL8531H 기능
기능 12 Bit 10MSPS ADC
제조업체 Samsung
로고 Samsung 로고


BL8531H 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.



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BL8531H 데이터시트, 핀배열, 회로
BL8531H
AFE FOR CCD/CIS SIGNAL PROCESSOR
GENERAL DESCRIPTION
The samsung analog front end(AFE) for CCD/CIS image signal is an integrated analog signal processor for color
image signal.
The AFE converts CCD/CIS output signal to digital data. The AFE includes three-channel CDS(Correlated
Double Sampling) circuit, PGA(Programmable Gain Amplifier), and 12-bit analog to digital converter with
reference generator.
A parallel data bus provides a simple interface to 8-bit microcontroller.
APPLICATIONS
Color and B/W Scanner
Digital Copiers
Facsimile
General Purpose CCD/CIS imager
FETURES
12-bit 6MSPS A/D Converter
Integrated Triple Correlated Double Sampler
3-Channel 2 MSPS Color Mode
Analog Programmble Gain Amplifier
Internal Voltage Reference
Wide clamp level controllability for CIS sensor
No Missing Code Guaranteed
Microcontroller-Compatible Control Interface
Operation by Single 5V Supply
CMOS Low Power Dissipation
KEY SPECIFICATION
Resolution: 12-bit
Conversion Rate: 6 MHz(2 MHz*3)
Supply Voltage: 5 V ± 5%
Power Dissipation: 375 mW(Typical)
1




BL8531H pdf, 반도체, 판매, 대치품
AFE FOR CCD/CIS SIGNAL PROCESSOR
CORE PIN CONFIGURATION
BL8531H
R_VIN
G_VIN
B_VIN
VSSA2
VDDA2
VSSA1
VDDA1
BGR REFT VCOM REFB
EXT_MCTL
MCTL1,MCTL2
VDDD
VSSD
VBB
STRTLN
bl8531h
D[11:0]/MPU[7:0]
AD[2:0]
CSB
WRB
RDB
OEB
ADCCLK
CDS1_CLK CDS2_CLK
ABSOLUTE MAXIMUM RATINGS
Charateritics
Supply Voltage
Analog Input Voltage
Digital Input Voltage
Digital Output Voltage
Reference Voltage
Storage Temperature Range
Operating Temperature Range
Symbol
VDD
AIN
CLK
VOH, VOL
VRT/VRB
Tstg
Topr
Value
6.5
VSS to VDD
VSS to VDD
VSS to VDD
VSS to VDD
-45 to 150
0 to 70
Units
V
V
V
V
V
°C
°C
NOTES:
1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently. Exposure to
ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied with
the other values kept within the following operating conditions and function operation under any of these conditions is not
implied.
2. All voltages are measured with respect to VSS unless otherwise specified.
3. 100pF capacitor is discharged through a 1.5kresistor (Human body model)
4

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BL8531H 전자부품, 판매, 대치품
BL8531H
AFE FOR CCD/CIS SIGNAL PROCESSOR
TIMING SPECIFICATIONS
(VDDA = 5V, VDDD = 5V unless otherwise noted)
Characteristics
3-Channel Conversion Rate
1-Channel Conversion Rate
CDSCLK1 Pulse Width
CDSCLK2 Pulse Width
CDSCLK2B Pulse Width
CDSCLK1 Falling to CDSCLK2 Rising
CDSCLK2 Falling to CDSCLK1 Rising
ADCCLK Pulse Width
CDSCLK2 Rising to ADCCLK Rising
CDSCLK2 Falling to ADCCLK Falling
ADCCLK Rising to CDS2CLK Falling
STRTLN Rising, Falling Setup & Hold
ADC Output Delay
Register Address Setup Time
Register Address Hold Time
Data Hold Time
Register Chip Select Setup Time
Register Chip Select Hold Time
Register Read Pulse Width
Write Pulse Width
Register Read To Data Valid
Output Enable High to Tri-State
Tri-State to Data Valid
Aperture Delay
Latency for 1 Channel mode
Symbol
tC1CLK
tC2CLK
tC2CLKB
tC1C2A
tC2C1A
tADCLK
tC2ADA
tC2ADB
tADC2A
tS, tH
tADDT
tAS
tAH
tDH
tCSS
tCSH
tPWR
tPWW
tDD
tHZ
tDEV
tAD
Min Typ Max Unit
500 ns
166 ns
60 ns
70 ns
70 ns
5 ns
5 ns
70 ns
70 ns
5 ns
5 ns
15 ns
20 ns
15 ns
15 ns
15 ns
15 ns
15 ns
50 ns
25 ns
40 ns
10 ns
15 ns
2 ns
4 ADCCL
K Cycles
* Aperture delay is a timing measurement between the sampling clocks and CDS. It is measured from the falling
edge of the CDS2_CLK input to when the input signal is held for data conversion
7

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