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EM4095 데이터시트 PDF




EM Microelectronic에서 제조한 전자 부품 EM4095은 전자 산업 및 응용 분야에서
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부품번호 EM4095 기능
기능 Read / Write Analog Front End
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EM4095 데이터시트, 핀배열, 회로
EM MICROELECTRONIC - MARIN SA
EM4095
Read/Write analog front end for 125kHz RFID Basestation
Description
The EM4095 (previously named P4095) chip is a CMOS
integrated transceiver circuit intended for use in an RFID
basestation to perform the following functions:
- antenna driving with carrier frequency
- AM modulation of the field for writable transponder
- AM demodulation of the antenna signal modulation
induced by the transponder
communicate with a microprocessor via simple interface.
Features
Integrated PLL system to achieve self adaptive
carrier frequency to antenna resonant frequency
No external quartz required
100 to 150 kHz carrier frequency range
Direct antenna driving using bridge drivers
Data transmission by OOK (100% Amplitude
Modulation) using bridge driver
Typical Operating Configuration
Read Only Mode
LA +5V
CRES
CDV1
+5V
CDV2
RDY/CLK
1 16
2 15
3 14
4 EPM44009955 13
5 12
6 11
7 10
89
CDC2
CFCAP
SHD
DEMOD_OUT
MOD
CAGND
CDEC
µP
Data transmission by Amplitude Modulation with
externally adjustable modulation index using single
ended driver
Multiple transponder protocol compatibility
(Ex: EM400X, EM4050, EM4150, EM4070, EM4170,
EM4069….)
Sleep mode 1µA
USB compatible power supply range
40 to +85°C temperature range
Small outline plastic package SO16
Applications
Car immobiliser
Hand held reader
Low cost reader
Pin Assignment
VSS
RDY/CLK
ANT1
DVDD
DVSS
ANT2
VDD
DEMOD_IN
SO16
DC2
FCAP
SHD
DEMOD_OUT
MOD
AGND
CDEC_IN
CDEC_OUT
Fig. 1
Read/Write Mode
LA +5V
CRES
CDV1
+5V
CDV2
RDY/CLK
1 16
2 15
3 14
4 EPM440095 13
5 12
6 11
7 10
89
CDC2
CFCAP
SHD
DEMOD_OUT
MOD
CAGND
CDEC
µP
Fig. 3
Fig. 2
Copyright 2002, EM Microelectronic-Marin SA
1
www.emmicroelectronic.com




EM4095 pdf, 반도체, 판매, 대치품
EM4095
Electrical and Switching Characteristics:
Parameters specified below are valid only in case the device is used according to Operating Conditions defined on previous
page.
VSS=DVSS=0V, VDD =DVDD = 5V, Tj = -40 to 110°C, unless otherwise specified
Parameter
Symbol Test Conditions
Min Typ Max Units
Supply current in sleep mode
Supply current excluding drivers
current
IDDsleep
IDDon
1 2 µA
5 7 mA
AGND level
VAGND Note 1
2.35 2.5 2.65 V
Logic signals SHD, MOD,
DEMOD_OUT
Input logic high
Input logic low
Output logic high
Output logic low
MOD pull down resistor
SHD pull up resistor
PLL
VIH
VIL
VOH
VOL
RPD
RPU
ISOURCE=1mA
ISINK=1mA
0.2VDD
0.8VDD
0.8VDD
V
0.2VDD
V
0.9VDD
V
0.1VDD
V
20 50 90 k
20 50 90 k
Antenna capture frequency range
Antenna locking frequency range
Drivers
FANT_C
FANT_L
100 150 kHz
100 150 kHz
ANT drivers output resistance
RDY/CLK driver output resistance
AM demodulation
RAD IANT=100mA
RCL IRDY/CLK=10mA
3 9
12 36
DEMOD_IN common mode range
VCM
VSS + 0.5
VDD - 0.5
V
DEMOD_IN input sensitivity
Vsense Note 2
0.85 2 mVpp
Note 1: AGND is a EM4095 internal reference point. Any external connection except specified capacitor to VSS may lead to
device malfunction.
Note 2: Modulating signal 2Khz square wave on 125 kHz carrier, total signal inside VCM
Vsense
Copyright 2002, EM Microelectronic-Marin SA
4
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EM4095 전자부품, 판매, 대치품
Signal RDY/CLK
This signal provides the external microprocessor with
clock signal which is synchronous with the signal on ANT1
and with information about EM4095 internal state. Clock
signal synchronous with ANT1 indicates that PLL is in lock
and that Reception chain operation point is set. When
SHD is high RDY/CLK pin is forced low. After high to low
transition on SHD the PLL starts-up, and the reception
chain is switched on. After time TSET the PLL is locked and
reception chain operation point has been established. At
this moment the same signal which is being transmitted to
ANT1 is also put to RDY/CLK pin indicating to
microprocessor that it can start observing signal on
DEMOD_OUT and giving at the same time reference
clock signal. Clock on RDY/CLK pin is continuous, it is
also present during time the ANT drivers are OFF due to
high level on MOD pin. During the time TSET from high to
low transition on SHD pin RDY/CLK pin is pulled down by
100 kpull down resistor. The reason for this is in
additional functionality of RDY/CLK pin in case of AM
modulation with index which is lower then 100%. In that
case it is used as auxiliary driver which maintains lower
amplitude on coil during modulation. (see also Typical
Operating Configuration)
Remark: Please refer to AN4095 for external components
calculation and limits.
Typical Operating Configuration
Read Only Mode
LA +5V
CRES
CDV1
+5V
CDV2
RDY/CLK
1 16
2 15
3 14
4 EPM44009955 13
5 12
6 11
7 10
89
CDC2
CFCAP
SHD
DEMOD_OUT
MOD
CAGND
CDEC
µP
Fig. 6
Read/Write mode (Low Q factor antenna)
LA +5V
CRES
CDV1
+5V
CDV2
RDY/CLK
1 16
2 15
3 14
4 EPM44009955 13
5 12
6 11
7 10
89
CDC2
CFCAP
SHD
DEMOD_OUT
MOD
CAGND
CDEC
µP
Fig. 7
Copyright 2002, EM Microelectronic-Marin SA
EM4095
Read/Write mode (High Q factor antenna)
RSER
LA +5V
CRES
CDV1
+5V
CDV2
RDY/CLK
1
2
C16 DC2
C15 FCAP
3
4
5
6
14
EPM44009955
13
12
11
SHD
DEMOD_OUT
MOD
CAGND
7 10 CDEC
89
µP
Read/Write mode (AM modulation)
Fig. 8
RAM
LA +5V
CRES
CDV1
+5V
CDV2
RDY/CLK
1
2
C16 DC2
C15 FCAP
3
4
5
6
14
EPM44009955 13
12
11
SHD
DEMOD_OUT
MOD
CAGND
7 10 CDEC
89
µP
Fig. 9
Figure 6 presents EM4095 used in Read Only mode. Pin
MOD is not used. It is recommended to connect it to VSS.
Figure 7 presents typical R/W configuration for OOK
communication protocol reader to transponder (eg.
EM4150). It is recommended to be used with low Q factor
antennas (up to 15).
When the antenna quality is high using configuration of
figure 6 or 7 the voltage on antenna can arrive in the
range of few hundred volts and antenna peak current may
exceed its maximum value. In such a case the capacitive
divider ratio has to be high thus limiting the sensitivity. For
such case it is better to reduce antenna circuit quality by
adding serial resistor. In this way the antenna current is
lower and thus power dissipation of IC is reduced with
practically the same performance (Fig. 8).
In the case AM modulation communication protocol
reader to transponder (eg. EM4069) is needed a single
ended configuration has to be used (figure 9). When pin
MOD is pulled high driver on ANT1 is put in three state,
driver RDY/CLK continues driving thus maintaining lower
antenna current. Modulation index is adjusted by resitor
RAM. As mentioned above RDY/CLK signal becomes
active only after the demodulation chain operating point is
set.
Before it is pulled down by high impedance pull down
resistor (100 k) in order not to load ANT1 output. In the
case of AM modulation configuration the total antenna
current change at the moment RDY/CLK pin becomes
active, so external microprocessor has to wait another
TSET before it can start observing DEMOD_OUT.
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