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MN6732741 데이터시트 PDF




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부품번호 MN6732741 기능
기능 Signal-processing IC for surveillance cameras and cameras for PC input
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MN6732741 데이터시트, 핀배열, 회로
Video Camera LSIs
MN6732741
Signal-processing IC for surveillance cameras and cameras for PC input
I Overview
The MN6732741 is camera signal-processing IC appropriate for a wide variety of applications, including
surveillance cameras and cameras used for input to personal computers. In addition to the basic functions of luminance
and chrominance signal processing, it also integrates the ALC, AWB, and AGC functions that were previously
implemented using microcontroller signal processing. Furthermore, it also integrates on a single chip, including SSG,
CG, and I2C-bus functions.
I Features
Input:
Analog signal (A/D converter input)
Outputs:
Digital output
8-bit YUV signal
Analog outputs
Luminance signal
Chrominance signal
Composite video signal output
RGB output
Operating supply voltage: 3.3 V ± 0.3 V
Operating clock frequency: 9.5 MHz to 28.7 MHz
Main functions
• 10-bit A/D converter
• Single-channel 10-bit D/A converter
• Two-channel 8-bit D/A converter
• Supports analog AGC (NN2038 or NN2039)
• CG and SSG circuits
• Supports 510 and 768 horizontal lines (NTSC and PAL)
• Supports VGA progressive scan readout CCDs (complementary color filters)
• Also supports black-and-white CCD signal processing
• CCD white defect/black defect correction circuit
• Digital AGC gain: up to 24 dB
• Left/right reversing function
• Variable gamma correction (γ = 0.3 to 1)
• ZV port standard mode, BT656 standard mode
• Modes: LL, SYNC, VD2, and HD/VD external synchronization support
• Built-in I2C-bus circuit
• ALC and AGC (Also supports external AGC)
• Two white balance modes (manual and ATW) with ATW lock function
• Automatic OB correction function
I Applications
Surveillance cameras, PC input cameras, multimedia cameras
Publication date: August 2001
SDB00060AEM
1




MN6732741 pdf, 반도체, 판매, 대치품
MN6732741
I Function Descriptions (by circuit block) (continued)
14. SSG
This block generates both low-speed pulse signals used by the CCD and various kinds of pulse signals used for
signal processing. (However, note that VBSGEN locking is not supported.)
15. I2C-bus
When power is first applied, the contents of an external EEPROM are read out and used to set the IC internal
registers.
Since this circuit does not support multi-master operation, no external devices will have become bus master
when power is first applied. This I2C-bus also can be used by external devices to read or write the IC internal registers.
(Note that certain limitations apply.)
I Pin Arrangement
COIN
OBCTL
EXTAGC
IRIS
ALCELC
ATWLOCK
APGAIN
BLCSW
DIN8
DIN7
DIN6
DIN5
DIN4
VDD4
VSS4
DIN3
DIN2
DIN1
DIN0
DS2
DS1
TESTDC2
TESTSW5
R
N.C.
TGVDD
TGVSS
N.C.
H2
N.C.
H1
N.C.
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
64 VIN
63 VREFL
62 VREFML
61 ADVDD
60 ADVSS
59 VREFM
58 VREFHM
57 VREFH
56 VREF23
55 IREF23
54 COMP23
53 BSIG
52 DAVSS1
51 DAVDD1
50 RSIG
49 VREF1
48 IREF1
47 COMP1
46 GSIG
45 DAVSS2
44 DAVDD2
43 VCXO
42 LPFI
41 FVR
40 MINTEST
39 SCANT
38 HREFCBLK
37 VCSYNCVD
36 YUVOE
35 NTPL
34 PCO
33 EXTMOD
(TOP VIEW)
4 SDB00060AEM

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MN6732741 전자부품, 판매, 대치품
MN6732741
I Pin Descriptions (continued)
Pin No.
Pin
I/O
Description
72 CCDSEL2
I CCD switching
73 RESET
I Logic system initial reset
74 SDA I/O I2C-bus (data)
75 SCL I/O I2C-bus (clock)
76 A0
I EEPROM address setting (pulled down)
77 A1
I EEPROM address setting (pulled down)
78 A2
I EEPROM address setting (pulled down)
79
VDD2
VDD Digital system power supply (3.3 V)
80
VSS2
VSS Digital system ground
81 PWM0 O PWM signal output
82 PWM1 O PWM signal output
83 PWM2 O PWM signal output
84 PWM3 O PWM signal output
85 YUV0 O Digital Y/UV output (LSB)
86 YUV1 O Digital Y/UV output
87 YUV2 O Digital Y/UV output
88 YUV3 O Digital Y/UV output
89 YUV4 O Digital Y/UV output
90 YUV5 O Digital Y/UV output
91 YUV6 O Digital Y/UV output
92 YUV7 O Digital Y/UV output (MSB)
93
VDD3
VDD Digital system power supply (3.3 V)
94
VSS3
VSS Digital system ground
95 FCKO O FCK output
96 FCK2O O 2FCK output
97 COIN
I Synchronization oscillator cell (LC oscillator)
98 OBCTL O OB automatic correction output
99 EXTAGC O External AGC control
100 IRIS
O Mechanical iris fixation (PWM output)
101 ALCELC
I Fixed/ELC switching. Low: ELC, High: Fixed
102 ATWLOCK
I ATW/Stop. Low: Normal, High: ATWLOCK
103 APGAIN
I Aperture gain switching. Low: Register value High: One half of the register value
104 BLCSW
I Backlighting correction. Low: Normal, High: ATWLOCK
105 DIN8
I Digital signal input (MSB)
106 DIN7
I Digital signal input
107 DIN6
I Digital signal input
108 DIN5
I Digital signal input
SDB00060AEM
7

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