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PDF ST63T73 Data sheet ( Hoja de datos )
| Número de pieza | ST63T73 | |
| Descripción | 8-BIT ROM/OTP/EPROM MCUs FOR DIGITALLY CONTROLLED MULTISYNC/MULTISTANDARD MONITORS | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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R ST6373
8-BIT ROM/OTP/EPROM MCUs FOR DIGITALLY
CONTROLLED MULTISYNC/MULTISTANDARD MONITORS
s 4.5V to 6V Operating Supply Voltage Range
s Low Current Consumption
s 0 to +70°C Operating Temperature Range
s 8 MHz clock Oscillator
s 16K bytes ROM/OTP/EPROM
(8K and 12K ROM versions also available)
s 192 bytes RAM
s 384 bytes general purpose EEPROM
s 128 bytes dedicated EEPROM for DDC SPI
s 22 fully programmable I/O pins, offering direct
LED drive capability, as well as interrupt
generation for keyboard inputs
s Digital WATCHDOG timer
s Three Timers, each comprising an 8-bit counter
and a 7- bit Prescaler
s SYNC Processor:
– 12-bits HSYNC Event Counter
– 12-bits VSYNC Period Counter
– HSYNC and VSYNC Polarity Detection
– HSYNC and VSYNC Outputs
– HFLYBACK and VFLYBACK Inputs
– CLAMP and BLANK Outputs
s 14-bit (PWM + BRM) D/A Converter
s Nine 7-bit PWM D/A Converter Outputs
s 8-bit A/D Converter with 8 multiplexed inputs
s DDC SPI with interrupt and 4 operating modes
s A further SPI with interrupt and 2 operating
modes
s Remote Control Signal Input (Non Maskable
Interrupt)
s VSYNC Interrupt Input
s Five Interrupt Vectors
s XOR Register (Instruction Set expansion)
s MIRROR Register (Instruction Set expansion)
PSDIP42
CSDIP42
(Refer to end of Document for Ordering Information)
February 1998
This is advance information from SGS-THOMS ON. Details are subject to change withoutnotice.
1/64
1
1 page  
Figure 1. ST6373 Block Diagram
TEST/VPP (**)
NMI
VS YNC
PW RIN
TEST
INTERRUPT
Inputs
TIMER 1
TIMER 2
DIGITAL
WATCHD OG/TIMER
USER PROGRAM
MEMORY
16 KBytes
DATA ROM
USER
SELECTABLE
DATA RAM
192 Bytes
DATA EEPROM
384 Bytes
PC
STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 3
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6
8 BIT CORE
POWER
SU PPLY
OSC ILLATOR
RESET
VDD VSS OSCin OSCout RESET
ST6373
PORT A
PORT B
PORT C
DDC SPI (1)
EEPROM
128 Bytes (1)
TIMER 3
SYNC
PROC ESSOR
I C SPI
D/A Outputs
A/D Inputs
PA0 -> PA7*
PB0 -> PB7*
PC0 -> PC7*
SCLD, SDAD
VSYNC, EXTCLK
HSYNC O, VSYNCO
HSYNC I, VSYNCI
HDRIV
HFLY, VFLY
CLMPO, BLKO
SCLI, SDAI
HDA, DA0 -> DA8
AD0 -> AD7
(*)Refer to Pin Description for Additional Information
(**)
V
PP
i nput
for
OTP/EPROM
device
programming
5/64
5 Page 
ST6373
MEMORY SPACES (Cont’d)
Data ROM Addressing. All the read-only data are
physically implemented in the ROM in which the
Program Space is also implemented. The ROM
therefore contains the program to be executed and
also the constants and the look-up tables needed
for the program. The locations of Data Space in
which the different constants and look-up tables
are addressed by the ST6 Core can be considered
as being a 64-byte window through which it is pos-
sible to access to the read-only data stored in the
ROM. This window is located from the 40h ad-
dress to the 7Fh address in the Data space and al-
lows the direct reading of the bytes from the 000h
address to the 03Fh address in the ROM. All the
bytes of the ROM can be used to store either in-
structions or read-only data. Indeed, the window
can be moved by step of 64 bytes along the ROM
in writing the appropriate code in the Write-only
Data ROM Window register (DRWR, location
C9h). The effective address of the byte to be read
as a data in the ROM is obtained by the concate-
nation of the 6 less significant bits of the address in
the Data Space (as less significant bits) and the
content of the DRWR (as most significant bits). So
when addressing location 40h of data space, and
0 is loaded in the DRWR, the physical addressed
location in ROM is 00h.
Data ROM Window Register (DWR)
Address: C9h - Write only
Reset Value: XXh
7
0
DWR7 DWR6 DWR5 DWR4 DWR3 DWR2 DWR1 DWR0
DWR7-DWR0. These are the Data Rom Window
bits that correspond to the upper bits of data ROM
program space. This register is undefined after re-
set.
Note:
Care is required when handling the DRWR as it is
write only. For this reason, it is not allowed to
change the DRWR contents while executing inter-
rupts drivers, as the driver cannot save and than
restore its previous content. If it is impossible to
avoid the writing of this register in interrupts driv-
ers, an image of this register must be saved in a
RAM location, and each time the program writes
the DRWR it writes also the image register. The
image register must be written first, so if an inter-
rupt occurs between the two instructions the
DRWR register is not affected.
Figure 6. Data ROM Window Memory Addressing
DATA ROM
13 12 11 10 9 8 7 6 5 4 3 2 1 0 PROGRAM SPACE ADDRESS
WINDOW REGISTER 7 6 5 4 3 2 1 0
READ
CONTENTS
(DWR)
5 4 3 2 1 0 DATA SPACE ADDRESS
01
40h-7Fh
IN INSTRUCTION
Example:
DWR=28h 0 0 1 0 1 0 0 0
DATA SPACE ADDRESS
0 10 1100 1
59h
ROM
ADDRESS:A19h 0 0 1 0 1 0 0 0 0 1 1 0 0 1
VR01573B
11/64
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