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ICX205AK 데이터시트 PDF




Sony에서 제조한 전자 부품 ICX205AK은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 ICX205AK 자료 제공

부품번호 ICX205AK 기능
기능 Diagonal 8mm (Type 1/2) Progressive Scan CCD Image Sensor
제조업체 Sony
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ICX205AK 데이터시트, 핀배열, 회로
ICX205AK
Diagonal 8mm (Type 1/2) Progressive Scan CCD Image Sensor with Square Pixel for Color Cameras
Description
The ICX205AK is a diagonal 8mm (Type 1/2)
interline CCD solid-state image sensor with a square
pixel array and 1.45M effective pixels. Progressive
scan allows all pixels' signals to be output
independently within approximately 1/7.5 second.
Also, the adoption of high frame rate readout mode
supports 30 frames per second. This chip features
an electronic shutter with variable charge-storage
time which makes it possible to realize full-frame still
image without a mechanical shutter. High resolution
and high color reproductivity are achieved through
the use of R, G, B primary color mosaic filters.
Further, high sensitivity and low dark current are
achieved through the adoption of HAD (Hole-
Accumulation Diode) sensors.
This chip is suitable for applications such as
electronic still cameras, PC input cameras, etc.
20 pin DIP (Cer-DIP)
Features
Progressive scan allows individual readout of the
image signals from all pixels.
High horizontal and vertical resolution (both approx.
800TV-lines) still image without a mechanical shutter.
Supports high frame rate readout mode
(effective 256 lines output, 30 frame/s)
Square pixel
Horizontal drive frequency: 14.318MHz
No voltage adjustments
(reset gate and substrate bias are not adjusted.)
R, G, B primary color mosaic filters on chip
High resolution, high color reproductivity,
high sensitivity, low dark current
Low smear, excellent antiblooming characteristics
Continuous variable-speed shutter
Pin 1
V
2
Pin 11
H
40
Optical black position
(Top View)
Device Structure
Interline CCD image sensor
Image size:
Total number of pixels:
Number of effective pixels:
Number of active pixels:
Chip size:
Unit cell size:
Optical black:
Number of dummy bits:
Substrate material:
Diagonal 8mm (Type 1/2)
1434 (H) × 1050 (V) approx. 1.50M pixels
1392 (H) × 1040 (V) approx. 1.45M pixels
1360 (H) × 1024 (V) approx. 1.40M pixels (7.959mm diagonal)
7.60mm (H) × 6.20mm (V)
4.65µm (H) × 4.65µm (V)
Horizontal (H) direction: Front 2 pixels, rear 40 pixels
Vertical (V) direction: Front 8 pixels, rear 2 pixels
Horizontal 20
Vertical 3
Silicon
2
8
Wfine CCD is a registered trademark of Sony Corporation.
Represents a CCD adopting progressive scan, primary color filter and square pixel.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E98118D3Z




ICX205AK pdf, 반도체, 판매, 대치품
ICX205AK
Absolute Maximum Ratings
Against φSUB
Against GND
Against VL
Between input
clock pins
Item
VDD, VOUT, φRG – φSUB
Vφ2A, Vφ2B φSUB
Vφ1, Vφ3, VL φSUB
Hφ1, Hφ2, GND – φSUB
CSUB φSUB
VDD, VOUT, φRG, CSUB – GND
Vφ1, Vφ2A, Vφ2B, Vφ3 – GND
Hφ1, Hφ2 – GND
Vφ2A, Vφ2B – VL
Vφ1, Vφ3, Hφ1, Hφ2, GND – VL
Voltage difference between vertical clock input pins
Hφ1 – Hφ2
Hφ1, Hφ2 – Vφ3
Storage temperature
Operating temperature
1 +24V (Max.) when clock width < 10µs, clock duty factor < 0.1%.
+16V (Max.) is guaranteed for turning on or off power supply.
Ratings
–40 to +10
–50 to +15
–50 to +0.3
–40 to +0.3
–25 to
–0.3 to +18
–10 to +18
–10 to +15
–0.3 to +28
–0.3 to +15
to +15
–16 to +16
–16 to +16
–30 to +80
–10 to +60
Unit Remarks
V
V
V
V
V
V
V
V
V
V
V 1
V
V
°C
°C
–4–

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ICX205AK 전자부품, 판매, 대치품
ICX205AK
Drive Clock Waveform Conditions
(1) Readout clock waveform
VT 100%
90%
II II
φM
10%
0%
VVT φM
2
tr twh tf
0V
Note) Readout clock is used by composing vertical transfer clocks Vφ2A and Vφ2B.
(2) Vertical transfer clock waveform
Vφ1
VVH1
VVHH
VVH
VVHL
VVL01
Vφ2A, Vφ2B
VVH02A, VVH02B
VVL1
VVLH
VVLL
VVHH
VVH2A, VVH2B
VVHL
VVL
VVH
Vφ3
VVL2A, VVL2B
VVLH
VVLL
VVH3
VVHL
VVHH
VVL
VVH
VVL03
VVLH
VVLL
VVH = VVH02A
VVL = (VVL01 + VVL03) / 2
VVL3 = VVL03
–7–
VVL
VφV1 = VVH1 – VVL01
VφV2A = VVH02A – VVL2A
VφV2B = VVH02B – VVL2B
VφV3 = VVH3 – VVL03

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