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ICX224AQ 데이터시트 PDF




Sony에서 제조한 전자 부품 ICX224AQ은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 ICX224AQ 자료 제공

부품번호 ICX224AQ 기능
기능 CCD Image Sensor with Square Pixel for Color Cameras
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ICX224AQ 데이터시트, 핀배열, 회로
ICX224AQ
Diagonal 8mm (Type 1/2) Frame Readout CCD Image Sensor with Square Pixel for Color Cameras
Description
The ICX224AQ is a diagonal 8mm (Type 1/2)
interline CCD solid-state image sensor with a square
pixel array and 2.02M effective pixels. Frame
readout allows all pixels' signals to be output
independently within approximately 1/7.5 second.
Also, the adoption of high frame rate readout mode
supports 30 frames per second which is four times
the speed in frame readout mode. This chip features
an electronic shutter with variable charge-storage
time. Adoption of a design specially suited for frame
readout ensures a saturation signal level equivalent
to when using field readout. High resolution and high
color reproductivity are achieved through the use of
R, G, B primary color mosaic filters. Further, high
sensitivity and low dark current are achieved through
the adoption of Super HAD CCD technology.
This chip is suitable for applications such as electronic
still cameras, PC input cameras, etc.
20 pin DIP (Plastic)
Pin 1
2
V
Features
Supports frame readout
High horizontal and vertical resolution
Supports high frame rate readout mode: 30 frames/s
4
Pin 11
H
48
Square pixel
Horizontal drive frequency: 18MHz
Optical black position
No voltage adjustments (reset gate and substrate bias are not adjusted.)
(Top View)
R, G, B primary color mosaic filters on chip
High color reproductivity, high sensitivity, low smear
Continuous variable-speed shutter
Low dark current, excellent anti-blooming characteristics
20-pin high-precision plastic package (top/bottom dual surface reference possible)
10
Device Structure
Interline CCD image sensor
Image size:
Diagonal 8mm (Type 1/2)
Total number of pixels: 1688 (H) × 1248 (V) approx. 2.11M pixels
Number of effective pixels: 1636 (H) × 1236 (V) approx. 2.02M pixels
Number of active pixels: 1620 (H) × 1220 (V) approx. 1.98M pixels
Chip size:
7.6mm (H) × 6.2mm (V)
Unit cell size:
3.9µm (H) × 3.9µm (V)
Optical black:
Horizontal (H) direction: Front 4 pixels, rear 48 pixels
Vertical (V) direction: Front 10 pixels, rear 2 pixels
Number of dummy bits: Horizontal 28
Vertical 1 (even fields only)
Substrate material:
Silicon
Super HAD CCD is a registered trademark of Sony Corporation. Super HAD CCD is a CCD that drastically improves sensitivity by introducing
newly developed semiconductor technology by Sony Corporation into Sony's high-performance HAD (Hole-Accumulation Diode) sensor
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E98927B99




ICX224AQ pdf, 반도체, 판매, 대치품
ICX224AQ
Bias Conditions
Item Symbol Min. Typ. Max. Unit Remarks
Supply voltage
VDD 14.55 15.0 15.45 V
Protective transistor bias
VL
1
Substrate clock
φSUB
2
Reset gate clock
φRG
2
1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same voltage as the VL power
supply for the V driver should be used.
2 Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated
within the CCD.
DC Characteristics
Item
Supply current
Symbol Min. Typ. Max. Unit Remarks
IDD 4.0 7.0 10.0 mA
Clock Voltage Conditions
Item
Symbol
Min.
Typ.
Max.
Unit
Waveform
diagram
Remarks
Readout clock voltage VVT
14.55 15.0 15.45 V
1
VVH1, VVH2
–0.05 0 0.05 V
2 VVH = (VVH1 + VVH2)/2
VVH3, VVH4
–0.2 0 0.05 V
2
VVL1, VVL2,
VVL3, VVL4
–8.0 –7.5 –7.0 V
2 VVL = (VVL3 + VVL4)/2
Vertical transfer clock
voltage
VφV
VVH3 – VVH
VVH4 – VVH
6.8 7.5 8.05 V
–0.25
0.1 V
–0.25
0.1 V
2 VφV = VVHn – VVLn (n = 1 to 4)
2
2
VVHH
1.4 V
2 High-level coupling
VVHL
1.3 V
2 High-level coupling
VVLH
1.4 V
2 Low-level coupling
VVLL
0.8 V
2 Low-level coupling
Horizontal transfer
clock voltage
VφH
VHL
VCR
4.75 5.0
–0.05 0
0.5 1.65
5.25
0.05
V
V
V
3
3
3 Cross-point voltage
Reset gate clock
voltage
VφRG
VRGLH – VRGLL
VRGL – VRGLm
3.0
3.3 5.25
0.4
0.5
V
V
V
4
4 Low-level coupling
4 Low-level coupling
Substrate clock voltage VφSUB
21.5 22.5 23.5 V
5
–4–

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ICX224AQ 전자부품, 판매, 대치품
ICX224AQ
(3) Horizontal transfer clock waveform
tr
Hφ2
twh
90%
tf
10%
Hφ1
VφH
VφH
2
two
VCR
twl
VHL
Cross-point voltage for the Hφ1 rising side of the horizontal transfer clocks Hφ1 and Hφ2 waveforms is VCR.
The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two.
(4) Reset gate clock waveform
tr twh
tf
RG waveform
VRGH
VRGLH
VRGLL
VRGLm
VφRG
Point A
twl
VRGL
VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from
Point A in the above diagram until the rising edge of RG.
In addition, VRGL is the average value of VRGLH and VRGLL.
VRGL = (VRGLH + VRGLL)/2
Assuming VRGH is the minimum value during the interval twh, then:
VφRG = VRGH – VRGL
Negative overshoot level during the falling edge of RG is VRGLm.
(5) Substrate clock waveform
100%
90%
VSUB
10%
0%
(A bias generated within the CCD)
VφSUB
tr twh
–7–
φM
φM
2
tf

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