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CH7013B 데이터시트 PDF




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부품번호 CH7013B 기능
기능 Digital PC to TV Encoder
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CH7013B 데이터시트, 핀배열, 회로
CCCCHHHRhRROrOoONNnNTTTtEeEELlLL
Digital PC to TV Encoder
CH7013B
1. FEATURES
• Universal digital interface accepts YCrCb (CCIR601
or 656) or RGB (15, 16 or 24-bit) video data in both
non-interlaced and interlaced formats
• True scale rendering engine supports underscan
operations for various graphics resolutions
• Enhanced text sharpness and adaptive flicker removal
with up to 5-lines of filtering
• Enhanced dot crawl control and area reduction
• Fully programmable through serial port
• Supports NTSC, NTSC-J, and PAL (B, D, G, H, I, M
and N) TV formats
• Provides Composite, S-Video and SCART outputs
• Auto-detection of TV presence
• Supports VBI pass-through
• Programmable power management
• 9-bit video DAC outputs
• Complete Windows and DOS driver software
• Offered in 48-pin LQFP
2. GENERAL DESCRIPTION
Chrontel’s CH7013B digital PC to TV encoder is a stand-
alone integrated circuit providing a robust solution for TV
output. It provides a universal digital input port to accept a
pixel data stream from a compatible VGA controller (or
equivalent) and converts it directly into the NTSC or PAL
TV format.
This device integrates a digital NTSC/PAL encoder with a 9-
bit DAC interface, an adaptive flicker filter, and a high
accuracy low-jitter phase locked loop to create outstanding
quality video. Through its true scale scaling and de-
flickering engine, the CH7013B supports full vertical and
horizontal underscan capability and operates in 5 different
resolutions including 640x480 and 800x600.
A universal digital interface along with full programmability
make the CH7013B ideal for system-level PC solutions. All
features are software programmable through a serial port to
enable a complete PC solution using a TV as the primary
display.
LINE
MEMORY
D[15:0]
PIXEL DATA
DIGITAL
INPUT
INTERFACE
RGB-YUV
CONVERTER
TRUE SCALE
SCALING & DEFLICKERING
ENGINE
YUV-RGB CONVERTER
NTSC/PAL
ENCODER
& FILTERS
TRIPLE
DAC
SYSTEM CLOCK
SERIAL CONTROL BLOCK
PLL
TIMING & SYNC GENERATOR
CLOCK
DATA
ADDR
XCLK
H V XI XO/FIN CSYNC P-OUT BCO
Figure 1: Functional Block Diagram
Y/R
C/G
CVBS/B
RSET
201-0000-069 Rev. 1.2, 9/1/2004
1




CH7013B pdf, 반도체, 판매, 대치품
CHRONTEL
Table 1. Pin Descriptions
48-Pin
LQFP
Type
Symbol
22 Out CVBS/B
19 Out CSYNC
29
In/Out
DATA
/SD
30 In CLOCK
/SL
32 In ADDR
38
Power
AGND
34
28
20, 26
Power
Power
Power
AVDD
VDD
GND
5, 18,
33, 42
8, 20,
31, 40
Power
Power
DVDD
DGND
CH7013B
Description
Composite Video Output
A 75 termination resistor with short traces should be attached between CVBS
and ground for optimum performance. In normal operating modes other than
SCART, this pin outputs the composite video signal. In SCART mode, this pin
outputs the blue signal.
Composite Sync Output
A 75 termination resistor with short traces should be attached between CSYNC
and ground for optimum performance. In SCART mode, this pin outputs the
composite sync signal.
Serial Data (External pull-up required)
This pin functions as the serial data pin of the serial interface port (see the serial
Port Operation section for details).
Serial Clock (Internal pull-up)
This pin functions as the serial clock pin of the serial interface port (see the serial
Port Operation section for details).
Serial Address Select (Internal pull-up)
This pin is the serial Address Select pin, which corresponds to bits 1 and 0 of the
serial device address, creating an serial port address selection as follows:
ADDR Serial Address Selected
1 111 0101 = 75h = 117
0 111 0110 = 76h = 118
NOTE: The serial port address is not to be confused with the Device Address Byte.
The Device Address Byte is composed of 8 bits rather than 7 bits where the first 7
bits is the serial port address and the last bit is the read/write bit. Please refer to
AN47 for details.
Analog ground
These pins provide the ground reference for the analog section of the CH7013B,
and MUST be connected to the system ground, to prevent latchup. Refer to the
Application Information section for information on proper supply de-coupling.
Analog Supply Voltage
These pins supply the +3.3V power to the analog section of the CH7013B.
DAC Power Supply
These pins supply the +3.3V power to CH7013B’s internal DAC’s.
DAC Ground
These pins provide the ground reference for CH7013B’s internal DACs. For
information on proper supply de-coupling, please refer to the Application
Information section.
Digital Supply Voltage
These pins supply the +3.3V power to the digital section of CH7013B.
Digital Ground
These pins provide the ground reference for the digital section of CH7013B, and
MUST be connected to the system ground to prevent latchup.
4 201-0000-069 Rev. 1.2, 9/1/2004

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CH7013B 전자부품, 판매, 대치품
CHRONTEL
CH7013B
Table 4. YCrCb Non-multiplexed Mode with Embedded Syncs
IDF#
Format
Pixel#
Bus Data
D[15]
D[14]
D[13]
D[12]
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
P0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
P1 P2
S[7] Y0[7]
S[6] Y0[6]
S[5] Y0[5]
S[4] Y0[4]
S[3] Y0[3]
S[2] Y0[2]
S[1] Y0[1]
S[0] Y0[0]
0 Cb0[7]
0 Cb0[6]
0 Cb0[5]
0 Cb0[4]
0 Cb0[3]
0 Cb0[2]
0 Cb0[1]
0 Cb0[0]
In this mode, the S[7-0] byte contains the following data:
1
YCrCb 16-bit
P3
Y1[7]
Y1[6]
Y1[5]
Y1[4]
Y1[3]
Y1[2]
Y1[1]
Y1[0]
Cr0[7]
Cr0[6]
Cr0[5]
Cr0[4]
Cr0[3]
Cr0[2]
Cr0[1]
Cr0[0]
P4
Y2[7]
Y2[6]
Y2[5]
Y2[4]
Y2[3]
Y2[2]
Y2[1]
Y2[0]
Cb2[7]
Cb2[6]
Cb2[5]
Cb2[4]
Cb2[3]
Cb2[2]
Cb2[1]
Cb2[0]
P5
Y3[7]
Y3[6]
Y3[5]
Y3[4]
Y3[3]
Y3[2]
Y3[1]
Y3[0]
Cr2[7]
Cr2[6]
Cr2[5]
Cr2[4]
Cr2[3]
Cr2[2]
Cr2[1]
Cr2[0]
P6
Y4[7]
Y4[6]
Y4[5]
Y4[4]
Y4[3]
Y4[2]
Y4[1]
Y4[0]
Cb4[7]
Cb4[6]
Cb4[5]
Cb4[4]
Cb4[3]
Cb4[2]
Cb4[1]
Cb4[0]
P7
Y5[7]
Y5[6]
Y5[5]
Y5[4]
Y5[3]
Y5[2]
Y5[1]
Y5[0]
Cr4[7]
Cr4[6]
Cr4[5]
Cr4[4]
Cr4[3]
Cr4[2]
Cr4[1]
Cr4[0]
S[6] =
S[5] =
S[4] =
F=
V=
H=
1 during field 2, 0 during field 1
1 during field blanking, 0 elsewhere
1 during EAV (the synchronization reference at the end of active video)
0 during SAV (the synchronization reference at the start of active video)
Bits S[7] and S[3:0] are ignored.
4.2 Multiplexed Mode
Each rising edge (or each rising and falling edge) of the XCLK signal will latch data from the graphics chip. The
multiplexed input data formats are shown in Figure 4 and 5. The Pixel Data bus represents an 8, 12, or 16-bit
multiplexed data stream, which contains either RGB or YCrCb formatted data. In IDF settings of 2, 4, 5, 7, 8, and 9,
the input data rate is 2X PCLK, and each pair of Pn values (e.g., P0a and P0b) will contain a complete pixel,
encoded as shown in the tables below. When IDF = 6, the input data rate is 3X PCLK, and each triplet of Pn values
(e.g., P0a, P0b and P0c) will contain a complete pixel, encoded as shown in the tables below. When the input is
YCrCb, the color-difference data will be transmitted at half the data rate of the luminance data, with the sequence
being set as Cb, Y, Cr, Y where Cb0,Y0,Cr0 refers to co-sited luminance and color-difference samples — and the
following Y1 byte refers to the next luminance sample, per CCIR656 standards. However, the clock frequency is
dependent upon the current mode, (not 27MHz, as specified in CCIR656).
201-0000-069 Rev. 1.2, 9/1/2004
7

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