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PDF MT4C4M4Bx Data sheet ( Hoja de datos )
| Número de pieza | MT4C4M4Bx | |
| Descripción | DRAM | |
| Fabricantes | Micron Technology | |
| Logotipo |  |
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DRAM
4 MEG x 4
FPM DRAM
MT4LC4M4B1, MT4C4M4B1
MT4LC4M4A1, MT4C4M4A1
For the latest data sheet, please refer to the Micron Web
site: www.micronsemi.com/mti/msp/html/datasheet.html
FEATURES
• Industry-standard x4 pinout, timing, functions,
and packages
• High-performance, low-power CMOS silicon-gate
process
• Single power supply (+3.3V ±0.3V or +5V ±0.5V)
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS#-ONLY, HIDDEN and CAS#-
BEFORE-RAS# (CBR)
• Optional self refresh (S) for low-power data
retention
• 11 row, 11 column addresses (2K refresh) or
12 row, 10 column addresses (4K refresh)
• FAST-PAGE-MODE (FPM) access
• 5V tolerant inputs and I/Os on 3.3V devices
OPTIONS
• Voltage
3.3V
5V
• Refresh Addressing
2,048 (2K) rows
4,096 (4K) rows
• Packages
Plastic SOJ (300 mil)
Plastic TSOP (300 mil)
• Timing
50ns access
60ns access
• Refresh Rates
Standard Refresh
Self Refresh (128ms period)
MARKING
LC
C
B1
A1
DJ
TG
-5
-6
None
S*
NOTE: 1. The 4 Meg x 4 FPM DRAM base number differenti-
ates the offerings in one place—MT4LC4M4B1. The
fifth field distinguishes various options: B1
designates a 2K refresh and A1 designates a 4K
refresh for FPM DRAMs.
2. The # symbol indicates signal is active LOW.
*Contact factory for availability
Part Number Example:
MT4LC4M4B1DJ
KEY TIMING PARAMETERS
SPEED
-5
-6
tRC
84ns
110ns
tRAC
50ns
60ns
tPC
20ns
35ns
tAA
25ns
30ns
tCAC
13ns
15ns
tRP
30ns
40ns
PIN ASSIGNMENT (Top View)
24/26-Pin SOJ
24/26-Pin TSOP
VCC
DQ0
DQ1
WE#
RAS#
**NC/A11
1
2
3
4
5
6
A10
A0
A1
A2
A3
VCC
8
9
10
11
12
13
26 VSS
VCC 1
25 DQ3
24 DQ2
23 CAS#
DQ0
DQ1
WE#
RAS#
2
3
4
5
22 OE# **NC/A11 6
21 A9
A10 8
19 A8
18 A7
17 A6
16 A5
15 A4
A0 9
A1 10
A2 11
A3 12
VCC 13
14 VSS
26 VSS
25 DQ3
24 DQ2
23 CAS#
22 OE#
21 A9
19 A8
18 A7
17 A6
16 A5
15 A4
14 VSS
**NC on 2K refresh and A11 on 4K refresh options.
4 MEG x 4 FPM DRAM PART NUMBERS
PART NUMBER
REFRESH
VCC ADDRESSING PACKAGE REFRESH
MT4LC4M4B1DJ-6 3.3V
2K
SOJ Standard
MT4LC4M4B1DJ-6 S 3.3V
2K
SOJ Self
MT4LC4M4B1TG-6 3.3V
2K
TSOP Standard
MT4LC4M4B1TG-6 S 3.3V
2K
TSOP
Self
MT4LC4M4A1DJ-6 3.3V
4K
SOJ Standard
MT4LC4M4A1DJ-6 S 3.3V
4K
SOJ Self
MT4LC4M4A1TG-6 3.3V
4K
TSOP Standard
MT4C4M4A1TG-6S 3.3V
4K
TSOP
Self
MT4C4M4B1DJ-6 5V
2K
SOJ Standard
MT4C4M4B1DJ-6 S 5V
2K
SOJ Self
MT4C4M4B1TG-6 5V
2K
TSOP Standard
MT4C4M4B1TG-6S 5V
2K
TSOP
Self
MT4C4M4A1DJ-6 5V
4K
SOJ Standard
MT4C4M4A1DJ-6 S 5V
4K
SOJ Self
MT4C4M4A1TG-6 5V
4K
TSOP Standard
MT4C4M4A1TG-6S 5V
4K
TSOP
Self
4 Meg x 4 FPM DRAM
D49_5V.p65 – Rev. 5/00
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
1 page  
4 MEG x 4
FPM DRAM
ICC OPERATING CONDITIONS AND MAXIMUM LIMITS
(Notes: 1, 2, 3, 5, 6) [Vcc (MIN) £ Vcc £ Vcc (MAX)]
PARAMETER/CONDITION
STANDBYCURRENT:TTL
(RAS# = CAS# = VIH)
STANDBY CURRENT: CMOS (non-“S” version only)
(RAS# = CAS# = other inputs = VCC - 0.2V)
STANDBY CURRENT: CMOS (“S” version only)
(RAS# = CAS# = other inputs = VCC - 0.2V)
OPERATINGCURRENT:RandomREAD/WRITE
Average power supply current
(RAS#, CAS#, address cycling: tRC = tRC [MIN])
OPERATING CURRENT: FAST PAGE MODE
Average power supply current
(RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN])
REFRESHCURRENT:RAS#-ONLY
Average power supply current
(RAS# cycling, CAS# = VIH: tRC = tRC [MIN])
REFRESHCURRENT:CBR
Average power supply current
(RAS#, CAS#, address cycling: tRC = tRC [MIN])
REFRESH CURRENT: Extended (“S” version only)
Average power supply current: CAS# = 0.2V or
CBR cycling; RAS# = tRAS (MIN); WE# = VCC - 0.2V;
A0-A11, OE# and DIN = VCC - 0.2V or 0.2V
(DIN may be left open)
REFRESH CURRENT: Self (“S” version only)
Average power supply current: CBR with
RAS# tRASS (MIN) and CAS# held LOW;
WE# = VCC - 0.2V; A0-A11, OE# and
DIN = VCC - 0.2V or 0.2V (DIN may be left open)
3.3V
5V
2K 4K 2K 4K
SYM SPEED REFRESH REFRESH REFRESH REFRESH UNITS NOTES
ICC1 ALL
1
1
1
1 mA
ICC2 ALL
500
500
500
500 mA
ICC2 ALL
150
150
150
150 µA
-5 110 90 140 120
ICC3 -6
100
80
130 110 mA 23
-5 110 100 110 100
ICC4 -6
100
90
100
90 mA 23
-5 110 90 140 120
ICC5 -6
100
80
130 110 mA
-5 110 90 140 120
ICC6 -6
100
80
130 110 mA 4, 7
ALL 300 300 300 300 µA 4, 7
ICC7
tRC 62.5 31.25 62.5 31.25 µs
23
ICC8 ALL
300
300
300
300 µA 4, 7
CAPACITANCE
(Note: 6)
PARAMETER
Input Capacitance: Address pins
Input Capacitance: RAS#, CAS#, WE#, OE#
Input/Output Capacitance: DQ
SYMBOL
CI1
CI2
CIO
MAX
5
7
7
UNITS
pF
pF
pF
4 Meg x 4 FPM DRAM
D49_5V.p65 – Rev. 5/00
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
5 Page 
4 MEG x 4
FPM DRAM
READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
RAS#
V
V
IH
IL
CAS#
V
V
IH
IL
ADDR
V
V
IH
IL
WE#
V
V
IH
IL
DQ
V
V
IOH
IOL
OE#
V
V
IH
IL
tCRP
tASR
tAR
tRAD
tRAH
ROW
tRWC
tRAS
tRCD
tCSH
tRSH
tCAS
tASC
tCAH
COLUMN
tRCS
tRWD
tCWD
tAWD
tCWL
tRWL
tWP
tCLZ
OPEN
tAA
tRAC
tCAC
tOE
tDS tDH
VALID D OUT
tOD
VALID D IN
tOEH
tRP
ROW
OPEN
DON’T CARE
UNDEFINED
TIMING PARAMETERS
SYMBOL
tAA
tAR
tASC
tASR
tAWD
tCAC
tCAH
tCAS
tCLZ
tCRP
tCSH
tCWD
tCWL
tDH
tDS
-5
MIN
MAX
25
38
0
0
42
13
8
8 10,000
0
5
38
28
8
8
0
MIN
45
0
0
49
10
10
0
5
45
35
10
10
0
-6
MAX
30
15
10,000
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
tOD
tOE
tOEH
tRAC
tRAD
tRAH
tRAS
tRCD
tRCS
tRP
tRSH
tRWC
tRWD
tRWL
tWP
-5
MIN
MAX
0 12
12
8
50
9
9
50 10,000
11
0
30
13
116
67
13
5
MIN
0
10
12
10
60
14
0
40
15
140
79
15
5
-6
MAX
15
15
60
10,000
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4 Meg x 4 FPM DRAM
D49_5V.p65 – Rev. 5/00
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet MT4C4M4Bx.PDF ] | |
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