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PDF IBM25PPC440GP Data sheet ( Hoja de datos )
| Número de pieza | IBM25PPC440GP | |
| Descripción | PowerPC 440GP Embedded Processor | |
| Fabricantes | IBM Microelectronics | |
| Logotipo |  |
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PowerPC 440GP Embedded Processor Data Sheet
Features
• PowerPC® 440 processor core operating up to
500MHz with 32KB I- and D-caches
• On-chip 8 KB SRAM
• Selectable processor:bus clock ratios of 3:1,
4:1, 5:1, 5:2, 7:2
• Double Data Rate (DDR) Synchronous DRAM
(SDRAM) 32/64-bit interface operating up to
133 MHz
• External Peripheral Bus for up to eight devices
with external mastering
• DMA support for external peripherals, internal
UART and memory
• PCI-X V1.0a interface (32 or 64 bits, up to
133MHz) with support for conventional PCI
V2.2
• Two Ethernet 10/100Mbps half- or full-duplex
interfaces. Operational modes supported are
MII, RMII, and SMII.
• Programmable Interrupt Controller supports
interrupts from a variety of sources.
• Programmable General Purpose Timers (GPT)
• Two serial ports (16750 compatible UART)
• Two IIC interfaces
• General Purpose I/O (GPIO) interface available
• JTAG interface for board level testing
• Internal Processor Local Bus (PLB) runs at
DDR SDRAM interface frequency
• Processor can boot from PCI memory
• Available in ceramic and plastic packages
Description
Designed specifically to address high-end
embedded applications, the PowerPC 440GP
(PPC440GP) provides a high-performance, low
power solution that interfaces to a wide range of
peripherals by incorporating on-chip power
management features and lower power dissipation.
This chip contains a high-performance RISC
processor core, DDR SDRAM controller,8KB
SRAM, PCI-X bus interface, Ethernet interfaces,
control for external ROM and peripherals, DMA with
scatter-gather support, serial ports, IIC interface,
and general purpose I/O.
Technology: IBM CMOS SA-27E, 0.18µm
(0.11 Leff), 5-layer metal
Packages: 25mm, 552-ball Ceramic Ball Grid Array
(CBGA) or Plastic Ball Grid Array (PBGA)
Power (estimated): Less than:
4.0W in normal mode
1.0 W in sleep mode
Supply voltages required: 3.3V, 2.5V, 1.8V
5/13/04
Page 1 of 72
1 page  
PowerPC 440GP Embedded Processor Data Sheet
Ordering and PVR Information
For information on the availability of the following parts, contact your local IBM sales office.
Product
Name
Order Part Number1
Processor
Frequency
Package
Rev
Level
PVR Value
JTAG ID
PPC440GP IBM25PPC440GP-3CC400C
400 MHz
25mm, 552 CBGA
C
0x40120481
0x22052049
PPC440GP IBM25PPC440GP-3CC400CZ 400MHz
25mm, 552 CBGA
C
0x40120481
0x22052049
PPC440GP IBM25PPC440GP-3CC400E
400 MHz
25mm, 552 CBGA
C
0x40120481
0x22052049
PPC440GP IBM25PPC440GP-3CC400EZ 400MHz
25mm, 552 CBGA
C
0x40120481
0x22052049
PPC440GP IBM25PPC440GP-3CC466C
466 MHz
25mm, 552 CBGA
C
0x40120481
0x22052049
PPC440GP IBM25PPC440GP-3CC466CZ 466MHz
25mm, 552 CBGA
C
0x40120481
0x22052049
PPC440GP IBM25PPC440GP-3CC500C
500 MHz
25mm, 552 CBGA
C
0x40120481
0x22052049
PPC440GP IBM25PPC440GP-3CC500CZ 500MHz
25mm, 552 CBGA
C
0x40120481
0x22052049
PPC440GP IBM25PPC440GP-3FC400C
400 MHz
25mm, 552 PBGA
C
0x40120481
0x22052049
PPC440GP IBM25PPC440GP-3FC400CZ 400MHz
25mm, 552 PBGA
C
0x40120481
0x22052049
PPC440GP IBM25PPC440GP-3FC400E
400 MHz
25mm, 552 PBGA
C
0x40120481
0x22052049
PPC440GP IBM25PPC440GP-3FC400EZ 400MHz
25mm, 552 PBGA
C
0x40120481
0x22052049
PPC440GP IBM25PPC440GP-3FC466C
466 MHz
25mm, 552 PBGA
C
0x40120481
0x22052049
PPC440GP IBM25PPC440GP-3FC466CZ 466MHz
25mm, 552 PBGA
C
0x40120481
0x22052049
PPC440GP IBM25PPC440GP-3FC500C
500 MHz
25mm, 552 PBGA
C
0x40120481
0x22052049
PPC440GP IBM25PPC440GP-3FC500CZ 500MHz
25mm, 552 PBGA
C
0x40120481
0x22052049
Notes:
1. Z at the end of the Order Part Number indicates a tape-and-reel shipping package. Otherwise, the chips are shipped in a tray.
Each part number contains a revision code. This is the die mask revision number and is included in the part
number for identification purposes only.
The PVR (Processor Version Register) and the JTAG ID register are software accessible (read-only) and
contain information that uniquely identifies the part. Refer to the PPC440GP User’s Manual for details on
accessing these registers.
Order Part Number Key
IBM25PPC440GP-3CC500Ex
IBM Part Number
Grade 3 Reliability
Package
C = Ceramic
F = Plastic
Shipping Package:
Blank = Tray
Z = Tape and reel
Case Temperature Range
C = -40°C to +85°C
E = -40°C to +105°C
Processor Speed
Revision Level
5/13/04
Page 5 of 72
5 Page 
PowerPC 440GP Embedded Processor Data Sheet
• Supports initiation of transfer to the following address spaces:
– Single beat I/O reads and writes
– Single beat and burst memory reads and writes
– Single beat configuration reads and writes (type 0 and type 1)
– Single beat special cycles
DDR SDRAM Memory Controller
The Double Data Rate (DDR) SDRAM memory controller supports industry standard 184-pin DIMMs and
other discrete devices. Up to four 512MB logical banks are supported in limited configurations. Global
memory timings, address and bank sizes, and memory addressing modes are programmable.
Features include:
• Registered and non-registered industry standard DIMMs and other discrete devices
• 32- or 64-bit memory interface with optional 8-bit ECC (SEC/DED)
• Sustainable 2.1GB/s peak bandwidth at 133MHz
• SSTL_2 logic
• 1 to 4 chip selects
• CAS latencies of 2, 2.5 and 3 supported
• PC200/266 support
• Page mode accesses (up to eight open pages) with configurable paging policy
• Programmable address mapping and timing
• Hardware and software initiated self-refresh
• Power management (self-refresh, suspend, sleep)
External Peripheral Bus Controller (EBC)
Features include:
• Up to eight ROM, EPROM, SRAM, Flash memory, and slave peripheral I/O banks supported
• Up to 66.66MHz operation (266MB/s)
• Burst and non-burst devices
• 8-, 16-, 32-bit byte-addressable data bus
• 32-bit address, 4GB address space
• Peripheral Device pacing with external “Ready”
• Latch data on Ready, synchronous or asynchronous
• Programmable access timing per device
– 256 Wait States for non-burst
– 32 Burst Wait States for first access and up to 8 Wait States for subsequent accesses
– Programmable CSon, CSoff relative to address
– Programmable OEon, WEon, WEoff (1 to 4 clock cycles) relative to CS
• Programmable address mapping
• External master interface
– Write posting from external master
– Read prefetching on PLB for external master reads
– Bursting capable from external master
– Allows external master access to all non-EBC PLB slaves
– External master can control EBC slaves for own access and control
5/13/04
Page 11 of 72
11 Page | ||
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