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ST2202 데이터시트 PDF




ETC에서 제조한 전자 부품 ST2202은 전자 산업 및 응용 분야에서
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부품번호 ST2202 기능
기능 8 BIT Integrated Microcontroller with 256K Bytes ROM
제조업체 ETC
로고 ETC 로고


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ST2202 데이터시트, 핀배열, 회로
ST
Sitronix
ST2202
PRELIMINARY
8 BIT Integrated Microcontroller with 256K Bytes ROM
Notice: This is not a final specification. Some parameters are subject to change.
1. FEATURES
„ Totally static 8-bit CPU
„ ROM: 256K x 8-bit
„ RAM: 4K x 8-bit
„ Stack: Up to 128-level deep
„ Operation voltage: 2.4V ~ 5.5V
„ Operation frequency:
„ Low Voltage Detector (LVD)
„ Memory interface to ROM, RAM, Flash
„ Memory configuration
– Three kinds of bank for program, data and interrupts
– 12-bit bank register supports up to 44M bytes
– 6 programmable chip-selects with 4 modes
– Maximum single device of 16M bytes at CS5
„ General-Purpose I/O (GPIO) ports
– 48 multiplexed CMOS bidirectional bit programmable
I/Os
– Hardware de-bounce option for Port-A
– Bit programmable pull-up for input pins
– Bit programmable pull-up/down and open-drain/CMOS
for Port-C
„ Programmable Watchdog Timer (WDT)
„ Timer/Counter
– Two 8-bit timer, one can be a 16-bit event counter
– One 8-bit Base timer with 5 coexistent interrupt time
settings
„ Three clocking outputs
– Clock sources including Timer0/1, baud rate generator
„ 11 prioritized interrupts with dedicated exception
vectors
– External interrupt (edge triggered)
– TIMER0 interrupt
– TIMER1 interrupt
– BASE timer interrupt
– PORTA interrupt (transition triggered)
– DAC reload interrupt
– LCD frame interrupt
– SPI interrupts (x2)
– UART interrupts (x2)
„ Dual clock sources with warm-up timer
– Low frequency crystal oscillator (OSCX)
····················································32768 Hz
– RC oscillator (OSC) ······························· 500K ~ 4M Hz
– High frequency crystal/resonator oscillator
(Bonding option)······ 455K~4M Hz
„ Direct Memory Access (DMA)
– Block-to-Block transfer
– Block to Single port
„ LCD Controller (LCDC)
– Software programmable screen size up to 240X120
(including 160x160, 160x80, etc.)
– Support 1-, 4-bit LCD data bus
– Share system memory with display memory
– Unique internal bus for memory sharing with no loss of
the CPU time
– Diverse functions including virtual screen , panning ,
scrolling , contrast control and alternating signal
generator
– Support software 16 gray levels
„ Universal Asynchronous Receiver/Transmitter (UART)
– Full-duplex operation
– Baud rate generator with one digital PLL
– Standard baud rates of 600 bps to 115.2 kbps
– Direct glueless support of IrDA physical layer protocol
– Two sets of I/Os (TX,RX) for two independent devices
„ Serial Peripheral Interface (SPI)
– Master and slave modes
– 5 serial signals including enable and data-ready
– One stage buffer for transmitter and receiver for
continuous data exchange
– Programmable data length from 7-bit to 16-bit
„ Programmable Sound Generator (PSG)
– Two channels with three playing modes
– Tone/noise generator
– 16-level volume control
– 8-bit PWM DAC for speech/voice
– Two dedicated outputs for directly driving and large
current
„ Three power down modes
– WAI0 mode
– WAI1 mode
– STP mode
Ver 2.0a
1/65
2003-May-05




ST2202 pdf, 반도체, 판매, 대치품
Sitronix
Function Group
External interrupt
Clocking output
GPIO
LCD controller
Pad No.
40
53~55
56~60
5~14
TABLE 3-2 Signal Function Groups (continued)
Designation
Description
INTX/PC0
External interrupt inputs
BCO/PE2 , TCO1/PE1 , Clocking outputs
TCO0/PE0
PE7~3
I/O port E
FLM/PL7, LOAD/PL6,
AC/PL5 , CP/PL4,
LD[3:0]/PL3~0, POFF ,
BLANK
LCD control signals
ST2202
Ver 2.0a
4/65
2003-May-05

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ST2202 전자부품, 판매, 대치품
Sitronix
ST2202
6. CPU
„ Register Model
70
A
70
Y
70
X
70
PCH
PCL
70
1S
Accumulator A
Index Register Y
Index Register X
Program Counter PC
Stack Pointer S
„ Accumulator (A)
The Accumulator is a general-purpose 8-bit register that stores
the results of most arithmetic and logic operations. In addition,
the accumulator usually contains one of the two data words
used in these operations.
„ Index Registers (X,Y)
There are two 8-bit Index Registers (X and Y), which may be
used to count program steps or to provide and index value to
be used in generating an effective address. When executing an
instruction, which specifies indexed addressing, the CPU
fetches the OP code and the base address, and modifies the
address by adding the index register to it prior to performing
the desired operation. Pre or post-indexing of indirect
addresses is possible.
direction of either the program or interrupts (IRQ). The stack
allows simple implementation of nested subroutines and
multiple level interrupts. The stack pointer is initialized by the
user’s software.
„ Program Counter (PC)
The 16-bit Program Counter register provides the address,
which step the microprocessor through sequential program
instructions. Each time the microprocessor fetches and
instruction from program memory, the lower byte of the
program counter (PCL) is placed on the low-order bits of the
address bus and the higher byte of the program counter (PCH)
is placed on the high-order 8 bits. The counter is increment
each time an instruction or data is fetched from program
memory.
„ Stack Pointer (S)
The Stack Pointer is an 8-bit register, which is used to control
the addressing of the variable-length stack. It’s range from
100H to 1FFH total for 256 bytes (128 level deep). The stack
pointer is automatically increment and decrement under control
of the microprocessor to perform stack manipulations under
„ Status Register (P)
The 8-bit Processor Status Register contains seven status flags.
Some of these flags are controlled by program; others may be
also controlled by the CPU as well. The instruction set contains
a member of conditional branch instructions that are designed
to allow testing of these flags. Refer to TABLE 6-1
TABLE 6-1 Status Register (P)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
NV1BD I Z
Bit 7: N : Signed flag by arithmetic
Bit 3: D : Decimal mode flag
1 = Negative
1 = Decimal mode
0 = Positive
0 = Binary mode
Bit 6: V : Overflow of signed Arithmetic flag
Bit 2: I : Interrupt disable flag
1 = Negative
1 = Interrupt disable
0 = Positive
0 = Interrupt enable
Bit 1: Z : Zero flag
1 = Zero
0 = Non zero
Bit 4: B : BRK interrupt flag
Bit 0: C : Carry flag
1 = BRK interrupt occur
1 = Carry
0 = Non BRK interrupt occur
0 = Non carry
Bit 0
C
Ver 2.0a
7/65
2003-May-05

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