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R65C51 데이터시트 PDF




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부품번호 R65C51 기능
기능 ASYNCHRONOUS COMMUNICATIONS INTERFACE ADAPTER
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R65C51 데이터시트, 핀배열, 회로
R65C51
ASYNCHRONOUS COMMUNICATIONS
DESCRIPTION
PRELiMlNARY
FEATURES
The Rockwell CMOS R65C51 Asynchronous Communications
Interface Adapter (ACIA) provides an easily implemented, pro-
gram controlled interface between 8-bit microprocessor-based
systems and serial communication data sets and modems.
The ACIA has an internal baud rate generator. This feature elim-
inates the need for multiple component support circuits, a crystal
being the only other part required. The Transmitter baud rate
can be selected under program control to be either 1 of 15 dif-
ferent rates from 50 to 19,200 baud, or at l/16 times an external
clock rate. The Receiver baud rate may be selected under pro-
gram control to be either the Transmitter rate, or at l/16 times
the external clock rate. The ACIA has programmable word
lengths of 5, 6, 7, or 8 bits; even, odd, or no parity; 1, 1'12, or
2 stop bits.
The ACIA is designed for maximum programmed control from
the microprocessor (MPU), to simplify hardware implementa-
tion. Three separate registers permit the MPU to easily select
the R65C51’s operating modes and’ data checking parameters
and determine operational status.
The Command Register controls parity, receiver echo mode,
transmitter interrupt control, the state of the RTS line, receiver
interrupt control, and the state of the DTR line.
Low power CMOS N-well silicon gate technology
Direct replacement for NMOS R6551 ACIA
Full duplex operation with buffered receiver and transmitter
Data set/modem control functions
Internal baud rate generator with 15 programmable bau
rates (50 to 19,200)
. Program-selectable internally or’externally controlled receive
rate
. Programmable word lengths, number of stop bits, and pant
bit generation and detection
Programmable interrupt control
Program reset
Program-selectable serial echo mode
Two chip selects
1 or 2 MI-Q operation
5.0 Vdc t 5% supply requirements
28-pin plastic or ceramic DIP
Full TTL compatibility
Compatible with. R6500, R6500/’ and R65COO micro-
processors
The Control Register controls the number of stop bits, word
length, receiver clock source, and baud rate.
--
The Status Register indicates the states of the IRQ, DSR, and
DCD lines. Transmitter and Receiver Data Registers, and
Overrun, Framing, and Parity Error conditions,
The Transmitter and Receiver Data Registers are used for tem-
porary data storage by the ACIA Transmit and Receiver circuits.
ORDERING INFORMATION
Part No.: R65C51
-
Temperature Range (TL to TH):
Blank = 0% to +70°C
E= -40% to +85%
Frequency Range:
1 = 1 MHz
2 = 2 MHz
Package:
C = Ceramic
P = Plastic
Document No. 29651 N60
2-296
Figure 1. R65C51 AClA Pin Configuration
Product Description Order No. 2157
Rev. 3, October 1984




R65C51 pdf, 반도체, 판매, 대치품
-
R65C5 1
Asynchronous Communications Interface Adapter (ACIA)
CONTROL REGISTER
Y antrot Register selects the desired baud rate, frequency
-. word length, and the number of stop bits.
76
54
c
WL
SBN ’
1 RCS
WLl WLO
32
1
S8R
SBR3 SBR2 SBRl
0
.
SBRO
\
Bit 7
i?
.
.
:
Stop Bit Number (SBN)
1 Stop bit
2 Stop bits
I 1:~Stop bits
For WL = 5 and no parity
1 Stop bit
For WL = 8 and parity
Bits 6-5
‘_3 r
3 -?
31
.0
.1
Word Length
No. Bits
8
7
6
5
(WL)
Bit 4
0
1
Receiver Clock Source (RCS)
External receiver clock
Baud rate
Bits 3-o
32
-Ti- 0
00
00
00
31
01
07
01
90
:0
10
10
11
?1
11
11
Selected Baud Rate (SBR)
1 0 Baud
0 016x
0 1 50
1 0 75
1 1 109.92
0 0 134.58
0 1 150
1 0 300
1 1 600
0 0 1200
0 1 1800
1 0 2400
1 1 3600
0 0 4800
0 1 7200
1 0 9600
1 1 19.200
?eset Initialization
76543210
o ooo0 00 0
‘ZJZFQ$j
Hardware reset (i%%)
Program reset
Selected Baud Rate (Bits 0, 1, 2, 3)
These bits select the Transmitter baud rate, which can be at
‘I16 an external clock rate or one of 15 other rates controlled by
the internal baud rate generator.
If the Receiver clock uses the same baud rate as the transmitter,
then RxC becomes an output and can be used to slave other
circuits to the ACIA. Figure 3 shows the Transmitter and Receiver
layout.
IRECEIVER
SHIFT REGISTER
I-_r
1J
RxD
.t
4
CLOCK
SYNC
* DIVIDER e LOGIC
(16)
RxC
XTU C
XTLOC
BIT 4
.
BAUD RATE +
GENERATOR
CLOCK
DIVIDER
(16)
f t t t,
1
r;;T;;:”
TRANSMITTER
1 SHIFT REGISTERI--
REGISTER
TxD
Figure 3. Transmitter/Receiver Clock Circuits
Receiver Clock Source (Bit 4)
This bit controls the clock source to the Receiver. A 0 causes
the Receiver to operate at a baud rate of l/16 an external clock.
A 1 causes the Receiver to operate at the same baud rate as
is selected for the transmitter.
Word Length (Bits 5, 6)
These bits determine the word length to be used (5, 6, 7 or 8
bits).
Stop Bit Number (Bit 7)
This bit determines the number of stop bits used. A 0 always
indicates one stop bit. A 1 indicates 1% stop bits if the word
length is 5 with no parity selected, 1 stop bit if the word length
is 8 with parity selected, and 2 stop bits in all other configurations.
m
2-299

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R65C51 전자부품, 판매, 대치품
R65C51
Asynchronous Communications Interface Adapter (ACIA
ACIA/MODEM INTERFACE
Crystal Pins (XTLI, XTLO)
These pins are normally directly connected to the parallel mode
external crystal (1.8432 MHz) to derive the various baud rates.
Alternatively, an externally generated clock can drive the XTLI
pin, in which case the XTLO pin must float. XTLI is the input
pin for the transmit clock.
Transmit Data (TxD)
The TxD output line transfers serial nonreturn-to-zero (NRZ)
data to the modem. The least significant bit (LSB) of the Transmit
Data Register is the first data bit transmitted and the rate of data
transmission is determined by the baud rate selected or under
control of an external clock. This selection is made by program-
ming the Control Register.
Receive Data (RxD)
The RxD input line transfers serial NRZ data into the ACIA from
‘the modem, LSB first. The receiver data rate is either the pro-
grammed baud rate or under the control of an externally gen-
erated receiver clock. The selection is made by programming
the Control Register.
Receive Clock (RxC)
The RxC is a bi-directional pin which is either the receiver 16x
clock input or the receiver 16x clock output. The latter mode
results if the internal baud rate generator is selected for receiver
data clocking.
Request to Send (m)
The m output pin controls the modem from the processor.
The state of the RTS pin is determined by the contents of the
Command Register.
Clear to Send (m)
The Cm input pin controls the transmitter operation. The enabl
state is with CTS low. The transmitter is automatically disable
if CTS is high.
Data Terminal Ready (m)
This output pin indicates the status of the ACIA to the moderr
A low on DTR indicates the ACIA is enabled, a high indicate:
it is disabled. The processor controls this pin via bit 0 of the
Command Register.
Data Set Ready (m)
The m input pin indicates to the ACIA the status of the
modem. A low indicates the “ready” state and a high, “not.
ready. ”
Data Carrier Detect (DCb)
The m input pin indicates to the ACIA the status of the carrier-
detect output of the modem. A low indicates that the modem
carrier signal is present and a high, that it is not.
TRANSMITTER AND RECEIVER OPERATION
Continuous Data Transmit
In the normal operating mode, the interrupt request output (m)
signals when the ACIA is ready to accept the next data word to
be transmitted. This interrupt occurs at the beginning of the Start
Bit. When the processor reads the Status Register of the ACIA,
the interrupt is cleared.
The processor must then identify that the Transmit Data Reg-
ister is ready to be loaded and must then load it with the next
data word. This must occur before the end of the Stop Bit, other-
wise a continuous “MARK” will be transmitted. Figure 5 shows
the continuous Data Transmit timing relationship.
CHAR=n
CHAR=n+l
CHAR =n+2
CHAR =cn+3
PROCESSOR
INTERRUPT
(TRANSMIT
REGISTER
/
OATA
EMPTY)
PROCESSOR.REAOSSTATUS
REGISTER, CAUSES IRO
TO CLEAR
PROCESSOR MUST
\ LOAONEWOATA
\ IN THIS TIME
INTERVAL;
OTHERWISE,
CONTINUOUS
“MARK”
IS TRANSMITTED
Figure 5. Continuous Data Transmit
2-302

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