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PDF AT2008 Data sheet ( Hoja de datos )
| Número de pieza | AT2008 | |
| Descripción | 8 Channel ADPCM Processor | |
| Fabricantes | Atelic Systems | |
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AT2008
8 Channels ADPCM Processor
Atelic Systems, Inc.
Description
AT2008 Application Note Preliminary
8 Channels ADPCM Processor
Version 1.0 January 29, 2001
The AT2008 is an eight full-duplex channels ADPCM processor. It follows the G.726 ITU Standard for ADPCM
compression for 40k, 32k, 24k and 16k bit rates with selectable µ-law and A-law input/output. This chip can operate on 16
channels of PCM to ADPCM compression, 16 channels of ADPCM to PCM decompression, 8 channels of full-duplex
operation in an 8KHz frame basis, or any combination of M-channels of compression plus N-channels of decompression
when M+N <= 16. Using the 3-wire command serial port, each individual half-channel can be dynamically configured to
perform the ADPCM algorithm at different bit rates, idle or reset of the algorithm. It can also be programmed to set up
different input/output time slots, or to select, (1) bypass without compression, (2) idle, or (3) reset of the algorithm.
Features
• 8 full channels of ITU G.726 ADPCM
• ADPCM coding and decoding with bypass mode
• Per channel selectable µ-Law and A-law input/output
• Up to 8 synchronous signals for direct interface with popular combo/codec.
• On-chip time slot assignment
• Available internal clock generator and frame sync. generator
• Simple 3-wire serial command port for chip configuration
• On-chip power-up/power down/reset
• The two clock pins (CLKA and CLKP) used as PCM/ADPCM data clocks, and the FSY pin used for Frame Sync signals
can be programmed to become either as input pins or as output pins. (The defaults are as input pins).
Applications
• DECT
• VoIP / VoDSL
• Wireless PBX systems
Default Settings
3-wire serial command is required to configure the chip running ADPCM in 8 full channels.
Page 1 of 19
©2001 Atelic Systems, Inc.
1 page  
AT2008
8 Channels ADPCM Processor
Power
The AT2008 is powered by a 3.3 V source and draws 100 mA at full operation and < 1 mA in powerdown mode.
Initialization
There are two different classes of resets available on the AT2008 chip. For the default reset, hold the RSTZ pin low for 50 ms. This reset
will bring the chip to a functioning default state. In the default state, the following parameters are set:
1. Pins FSY, CLKP, CLKA default to input (chip will receive these signals from external source)
2. 4 half channels of 32k µ-law ADPCM decoder running on half channels 0-3
3. 4 half channels of 32k µ -law ADPCM encoder running on half channels 4-7
A second type of reset involving the use of the 3-wire serial interface can also be used direct the pin I/O configurations of FSY, CLKP,
and CLKA during reset.
Page 5 of 19
©2001 Atelic Systems, Inc.
5 Page 
Reference Designs and Additional Notes
Using the AT2008 with other combo chips
Combo 0
DX
DR
Combo 1
Combo 2
Combo 3
AT2008
8 Channels ADPCM Processor
AT2008
XIN(16)
FSY(25)
SYNC.1(18)
YOUT(24)
CLKP(17)
SYNC2(15)
SYNC3(11)
SYNC4(10)
(20)XOUT
(27)YIN
CLKA
TM1
TM0
SDI SCLK SCSZ
Note:
SDI, SCLK, SCSZ are for 3-wire commands and should be connected to microcontroller I/O pins.
CLKA and FSY.
Typical application of default setting uses National single channel Combo (Quad Combo can be used to replace
the 4 single Combo)
When there are multiple AT2008 used on the same systems, A1, A0 are used to identify the chip.
A1, A0 are for chip ID. Values are from 00-03. They should be connected to microcontroller I/O lines or wired to either
VCC or ground.
Page 11 of 19
©2001 Atelic Systems, Inc.
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet AT2008.PDF ] | |
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