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C1851BCU 데이터시트 PDF




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C1851BCU 데이터시트, 핀배열, 회로
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DATA SHEET
BIPOLAR ANALOG INTEGRATED CIRCUIT
µPC1851B
I2C BUS-COMPATIBLE US MTS PROCESSING LSI
The µPC1851B is an integrated circuit for US MTS (Multiplexed Television Sound) system with the addition of
the I2C bus interface. All functions required for US MTS system are incorporated on a single chip.
The µPC1851B allows users to switch modes, control volume and tone, and adjust the separation circuit
through the I2C bus.
FEATURES
• Stereo demodulation, SAP (Sub Audio Program) demodulation, dbx noise reduction decoding, I2C bus interface,
input selector (2 channels), surround processor (1 phase), volume and tone control circuits incorporated on a single
chip
• Mode switching, volume and tone control, and separation adjustment through the I2C bus
• Power supply: 8 V to 10 V
• On-chip input attenuator for simple interface with intermediate frequency processing IC (I2C bus control)
• Output level: 1.4 Vp-p (with L+R signals, 100 % modulation)
APPLICATION
• TV sets and VCRs for north America
ORDERING INFORMATION
Part Number
µPC1851BCU
Package
42-pin plastic SDIP (15.24 mm (600))
The µPC1851B is available only to licensees of THAT Corporation.
For information, please call: (508) 229-2500 (U.S.A), or (03) 5790-5391 (Tokyo).
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. S13417EJ2V0DS00 (2nd edition)
Date Published June 2000 N CP(K)
Printed in Japan
The mark shows major revised points.
©
1998




C1851BCU pdf, 반도체, 판매, 대치품
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STEREO DEMODULATION BLOCK
µPC1851B
From Input Attenuator
φ D1 φD2 PD1 PD2
5 6 34
Stereo Phase
Comparator
D/A
Stereo
VCO
Divider
11
42
Stereo LPF
Pilot Discrimination
Phase Comparator
To I2C bus Interface
Pilot Canceler
L–R AM
Demodulator
To L+R LPF
To Switch
SAP DEMODULATION BLOCK
From Input Attenuator
SAP BPF
To Noise BPF
SOA 12
Offset Absorption
SDT 8
SAP Detector
To I2C bus Interface
Phase Detector Loop Filter
SAP VCO
D/A
SAP LPF
10
SOT
4 Data Sheet S13417EJ2V0DS00

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C1851BCU 전자부품, 판매, 대치품
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PIN CONFIGURATION (Top View)
42-pin plastic SDIP (15.24 mm (600))
µPC1851BCU
Power Supply (9 V)
1
2
Vcc Filter
1 VCC
2 VRE
Pilot Discrimination Filter 1 3 PD1
Pilot Discrimination Filter 2
Phase Comparator Filter 1
4 PD2
5 φ D1
Phase Comparator Filter 2 6 φ D2
Composite Signal Input 7 COM
SAP Discrimination Filter 8 SDT
Noise Detector Filter 9 NDT
SAP Single Output 10 SOT
SAP Single Input 11 SI
SAP Offset Absorption 12 SOA
Spectral RMS Timing 13 STI
Spectral RMS Offset Absorption 14 SRB
Timing Current Setting 15 ITI
Wide-band RMS Timing 16 WTI
Wide-band RMS Offset Absorption 17 WRB
Variable Emphasis Offset Absorption 18 dO
Volume Control Offset Absorption 19 VOL-C
VCA Offset Absorption 20 VOA
Analog GND 21 AGND
µPC1851B
MOA 42 Monaural Offset Absorption
FOL 41 L-channel Fixed Output
FOR 40 R-channel Fixed Output
EL1 39 External L-channel Input 1
ER1 38 External R-channel Input 1
EL2 37 External L-channel Input 2
ER2 36 External R-channel Input 2
MOL 35 L-channel Matrix Output
MOR 34 R-channel Matrix Output
LBC 33 L-channel Capacity of Low Frequency Band Width
LTC 32 L-channel Capacity of High Frequency Band Width
TLO 31 L-channel Offset Absorption
RBC 30 R-channel Capacity of Low Frequency Band Width
RTC 29 R-channel Capacity of High Frequency Band Width
TRO 28 R-channel Offset Absorption
SUR 27 Surround Timing
LOT 26 L-channel Output
ROT 25 R-channel Output
DGND 24 Digital GND (for I2C bus)
SCL 23 SCL (for I2C bus)
SDA 22 SDA (for I2C bus)
Data Sheet S13417EJ2V0DS00
7

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