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ICX278AL 데이터시트 PDF




Sony Corporation에서 제조한 전자 부품 ICX278AL은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 ICX278AL 기능
기능 Diagonal 4.5mm (Type 1/4) CCD Image Sensor for EIA B/W Video Cameras
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ICX278AL 데이터시트, 핀배열, 회로
ICX278AL
Diagonal 4.5mm (Type 1/4) CCD Image Sensor for EIA B/W Video Cameras
Description
The ICX278AL is an interline CCD solid-state
image sensor suitable for EIA B/W video cameras
with a diagonal 4.5mm (Type 1/4) system. Compared
with the current product ICX208AL, basic
characteristics such as sensitivity, smear and
dynamic range are improved drastically from visible
light region to near infrared light region through the
adoption of EXview HAD CCDTM technology.
This chip features a field period readout system and
an electronic shutter with variable charge-storage time.
The package is a 10mm-square 14-pin DIP (Plastic).
14 pin DIP (Plastic)
Features
Sensitivity in near infrared light region
(+5dB compared with the ICX208AL, λ = 945nm)
High sensitivity (+6dB compared with the ICX208AL, no IR cut filter)
Low smear (–20dB compared with the ICX208AL)
High D range (+2dB compared with the ICX208AL)
Horizontal register: 3.3 to 5V drive
Reset gate:
3.3 to 5V drive
No voltage adjustment
(Reset gate and substrate bias are not adjusted.)
High resolution and low smear
Excellent antiblooming characteristics
Continuous variable-speed shutter
Recommended range of exit pupil distance: –20 to –100mm
Pin 1
2
V
3
Pin 8
H
12
40
Optical black position
(Top View)
Device Structure
Interline CCD image sensor
Image size:
Diagonal 4.5mm (Type 1/4)
Number of effective pixels: 768 (H) × 494 (V) approx. 380K pixels
Total number of pixels: 811 (H) × 508 (V) approx. 410K pixels
Chip size:
4.43mm (H) × 3.69mm (V)
Unit cell size:
4.75µm (H) × 5.55µm (V)
Optical black:
Horizontal (H) direction : Front 3 pixels, rear 40 pixels
Vertical (V) direction : Front 12 pixels, rear 2 pixels
Number of dummy bits: Horizontal 22
Vertical 1 (even fields only)
Substrate material:
Silicon
TM
EXview HAD CCD is a trademark of Sony Corporation.
EXview HAD CCD is a CCD that drastically improves light efficiency by including near infrared light region as a basic structure of
HAD (Hole-Accumulation-Diode) sensor.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E00Z50A3Z




ICX278AL pdf, 반도체, 판매, 대치품
ICX278AL
Bias Conditions
Item Symbol Min. Typ. Max. Unit Remarks
Supply voltage
Protective transistor bias
Substrate clock
Reset gate clock
VDD
VL
φSUB
φRG
14.55
15.0
1
2
2
15.45
V
1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL
power supply for the V driver should be used.
2 Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated
within the CCD.
DC Characteristics
Item
Supply current
Symbol Min. Typ. Max. Unit Remarks
IDD 4 6 mA
Clock Voltage Conditions
Item
Symbol
Min.
Readout clock voltage
Vertical transfer clock
voltage
Horizontal transfer
clock voltage
VVT
VVH1, VVH2
VVH3, VVH4
VVL1, VVL2,
VVL3, VVL4
VφV
VVH3 – VVH
VVH4 – VVH
VVHH
VVHL
VVLH
VVLL
VφH
VHL
14.55
–0.05
–0.2
–8.0
6.3
–0.25
–0.25
3.0
–0.05
Reset gate clock
voltage
VφRG
3.0
VRGLH – VRGLL
VRGL – VRGLm
Substrate clock voltage VφSUB
21.0
Typ.
15.0
0
0
–7.0
7.0
3.3
0
3.3
22.0
Max.
Unit
Waveform
diagram
Remarks
15.45 V
1
0.05 V
2 VVH = (VVH1 + VVH2)/2
0.05 V
2
–6.5 V
2 VVL = (VVL3 + VVL4)/2
8.05 V
0.1 V
0.1 V
0.3 V
0.3 V
0.3 V
0.3 V
5.25 V
0.05 V
5.5 V
0.4 V
0.5 V
23.5 V
2 VφV = VVHn – VVLn (n = 1 to 4)
2
2
2 High-level coupling
2 High-level coupling
2 Low-level coupling
2 Low-level coupling
3
3
4
Input through 0.1µF
capacitance
4 Low-level coupling
4 Low-level coupling
5
–4–

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ICX278AL 전자부품, 판매, 대치품
ICX278AL
(3) Horizontal transfer clock waveform
tr
twh
tf
90%
10%
VHL
(4) Reset gate clock waveform
VφH
RG waveform
VRGLH
VRGLL
VRGLm
Hφ1 waveform
VφH/2 [V]
twl
Point A
twl
tr twh tf
VRGH
VφRG
VRGL
VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from
Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and
VRGLL.
VRGL = (VRGLH + VRGLL)/2
Assuming VRGH is the minimum value during the interval twh, then:
VφRG = VRGH – VRGL
Negative overshoot level during the falling edge of RG is VRGLm.
(5) Substrate clock waveform
100%
90%
10%
VSUB
0%
(A bias generated within the CCD)
VφSUB
tr twh
–7–
tf
φM
φM
2

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