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ICX278AK 데이터시트 PDF




Sony Corporation에서 제조한 전자 부품 ICX278AK은 전자 산업 및 응용 분야에서
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부품번호 ICX278AK 기능
기능 Diagonal 4.5mm (Type 1/4) CCD Image Sensor for NTSC Color Video Cameras
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ICX278AK 데이터시트, 핀배열, 회로
ICX278AK
Diagonal 4.5mm (Type 1/4) CCD Image Sensor for NTSC Color Video Cameras
Description
The ICX278AK is an interline CCD solid-state
image sensor suitable for NTSC color video cameras
with a diagonal 4.5mm (Type 1/4) system. Compared
with the current product ICX208AK, basic
characteristics such as sensitivity, smear and
dynamic range are improved drastically through the
adoption of EXview HAD CCDTM technology.
This chip features a field period readout system and
an electronic shutter with variable charge-storage time.
The package is a 10mm-square 14-pin DIP (Plastic).
EXview HAD CCDTM has different spectral
characteristics from the current CCD.
14 pin DIP (Plastic)
Features
High sensitivity (+5dB compared with the ICX208AK)
Low smear (–20dB compared with the ICX208AK)
High D range (+2dB compared with the ICX208AK)
Horizontal register: 3.3 to 5.0V drive
Reset gate:
3.3 to 5.0V drive
No voltage adjustment
(Reset gate and substrate bias are not adjusted.)
High resolution, low smear and low dark current
Excellent antiblooming characteristics
Continuous variable-speed shutter
Recommended range of exit pupil distance: –20 to –100mm
Ye, Cy, Mg, and G complementary color mosaic filters on chip
Pin 1
2
V
3
Pin 8
H
12
40
Optical black position
(Top View)
Device Structure
Interline CCD image sensor
Image size:
Diagonal 4.5mm (Type 1/4)
Number of effective pixels: 768 (H) × 494 (V) approx. 380K pixels
Total number of pixels: 811 (H) × 508 (V) approx. 410K pixels
Chip size:
4.43mm (H) ×3.69mm (V)
Unit cell size:
4.75µm (H) × 5.55µm (V)
Optical black:
Horizontal (H) direction: Front 3 pixels, rear 40 pixels
Vertical (V) direction: Front 12 pixels, rear 2 pixels
Number of dummy bits: Horizontal 22
Vertical 1 (even fields only)
Substrate material:
Silicon
TM
EXview HAD CCD is a trademark of Sony Corporation.
EXview HAD CCD is a CCD that drastically improves light efficiency by including near infrared light region as a basic structure of
HAD (Hole-Accumulation-Diode) sensor.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E00Z49-PS




ICX278AK pdf, 반도체, 판매, 대치품
ICX278AK
Clock Equivalent Circuit Constant
Item Symbol
Capacitance between vertical transfer clock
and GND
CφV1, CφV3
CφV2, CφV4
CφV12, CφV34
Capacitance between vertical transfer clocks
CφV23, CφV41
CφV13
CφV24
Capacitance between horizontal transfer clock
and GND
CφH1, CφH2
Capacitance between horizontal transfer clocks CφHH
Capacitance between reset gate clock and GND CφRG
Capacitance between substrate clock and GND CφSUB
Vertical transfer clock series resistor
R1, R2, R3, R4
Vertical transfer clock ground resistor
RGND
Horizontal transfer clock series resistor
RφH
Reset gate clock series resistor
RφRG
Min.
Typ.
1200
560
220
120
82
75
22
36
5
180
82
15
12
51
Max.
Unit Remarks
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
Vφ1
R1
CφV12
Vφ2
R2
CφV41
CφV1
CφV2
CφV23
CφV24
R4
CφV4 RGND CφV3
CφV34
CφV13
R3
Vφ4 Vφ3
RφH
Hφ1
CφH1
CφHH
RφH
Hφ2
CφH2
Vertical transfer clock equivalent circuit
Horizontal transfer clock equivalent circuit
RGφ
RφRG
CφRG
Reset gate clock equivalent circuit
4

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ICX278AK 전자부품, 판매, 대치품
ICX278AK
Clock Switching Characteristics
twh twl
tr
tf
Item Symbol
Unit Remarks
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
Readout clock
VT
2.3 2.5
0.5
0.5
µs
During
readout
Vertical transfer
clock
Vφ1, Vφ2,
Vφ3, Vφ4
15 250 ns 1
During
Hφ1 26 28.5 26 28.5
imaging
Hφ2
26 28.5
26 28.5
6.5 9.5
6.5 9.5
6.5 9.5 ns 2
6.5 9.5
During
Hφ1
parallel-serial
conversion Hφ2
5.38
5.38
0.01
0.01
0.01
µs
0.01
Reset gate clock φRG
11 13
51
3
3 ns
Substrate clock φSUB
1.5 1.8
0.5
0.5
µs
During drain
charge
1 When vertical transfer clock driver CXD1267AN is used.
2 When VφH = 3.0V. tf tr 2ns, and the cross-point voltage (VCR) for the Hφ1 rising side of the Hφ1 and Hφ2
waveforms must be at least VφH/2 [V].
Item Symbol
Horizontal transfer clock Hφ1, Hφ2
two
Unit Remarks
Min. Typ. Max.
22 26
ns 3
3 The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two.
7

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