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ATC18RHA PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 ATC18RHA
기능 Rad. Hard 0.18 Um CMOS Cell-based ASIC for Space Use
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ATC18RHA 데이터시트, 핀배열, 회로
Features
Comprehensive Library of Standard Logic and I/O Cells
ATC18RHA Core and I/O Cells Designed to Operate with VDD = 1.8V Sparing 0.15V as
Main Target Operating Conditions
IO33 Pad Libraries Provide Interfaces to 3V Environments
Memory Cells Compiled to the Precise Requirements of the Design
EDAC Library
SEU Hardened DFF’s
Cold Sparring Buffers
High Speed LVDS Buffers
PCI Buffers
Predefined Die Sizes to Accommodate Specified Packages and ESA (European Space
Agency) Multi-project Wafer Services
MQFP Package Up to 352 Pins (340 Signal Pins)
MCGA Packages Up to 625 Pins (581 Signal Pins)
Assurance Programs Will Allow
– Testing Flight Models to SCC B and QML Q & V
– Monitoring Heavy Ions Latch-up Immunity and Total Dose Capability Better than
100 Krads.
Description
The Atmel ATC18RHA is fabricated on a proprietary 0.18 µm, up to six-layer-metal
CMOS process intended for use with a supply voltage of 1.8V ± 0.15V. Table 1 shows
the range for that Atmel library cells have been characterized.
Table 1. Recommended Operating Conditions
Symbol Parameter
Conditions
Min Typ Max Unit
VDD
VDD3.3
VI
VO
TEMP
DC Supply Voltage Core and Standard I/Os 1.65 1.8 1.95
DC Supply Voltage 3V Interface I/Os
3 3.3 3.6
DC Input Voltage
DC Output Voltage
Operating Free Air
Temperature Range
Military
0 VDD
0 VDD
-55 +125
V
V
V
V
°C
The Atmel cell libraries and megacell compilers have been designed in order to be
compatible with each other. Simulation representations exist for three types of operat-
ing conditions. They correspond to three characterization conditions defined as
follows:
• MIN conditions:
– TJ = -55°C
– VDD (cell) = 1.95V
– Process = fast
• TYP conditions:
– TJ = +25°C
– VDD (cell) = 1.8V
– Process = typ
• MAX conditions:
– TJ = +125°C
– VDD (cell) = 1.65V
– Process = slow
Rad. Hard
0.18 µm CMOS
Cell-based ASIC
for Space Use
ATC18RHA
Advance
Information
Rev. 4261A–AERO–07/03
1




ATC18RHA pdf, 반도체, 판매, 대치품
Input/Output Pad Cell
Libraries
IO18lib and IO33lib
The Atmel Input/Output Cell Library, IO18lib, contains a comprehensive list of input, out-
put, bi-directional and tri-state cells. The ATC18RHA (1.8V) cell library includes one
special sets of I/O cells and IO33lib, for interfacing with external 3.3V devices.
They will encompass the following types of cells:
• bi-directional
• tri-state outport
• outputs
• inputs
• PCI
• PECL
• LVDS (EIA-644)
All buffers will be capable of being used as “Cold Sparing” Buffers.
Compiled Memories
Based on Virage Logic Memory Compilers, for synchronized memories. Its maximum
memory size compilation capability is:
SRAM
DPRAM
TPSF
16K x 32 bits
8K x 32 bits
1K x 16 bits
A set of EDAC can be used in combination with these memories so as to alleviate their
SEU susceptibility.
Synthesized Memory
The synthesis of memories is based on Atmel GENESYS within the GATEAID software.
It must be used only for small memories and when SEU hardened cells are needed.
The maximum memory sizes are as follows:
RAM
TPRAM
DPRAM
4K bits
4K bits
2K bits
4 ATC18RHA
4261A–AERO–07/03

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ATC18RHA 전자부품, 판매, 대치품
ATC18RHA
Activities
Final Verifications
Function
Static Timing
Analysis
Equivalence
Checking
Back-annotated
Simulation
Consumption
Analysis
Power Scheme
Check
Test Patterns
Gdsii Generation
Cross-talk Analysis
Cross-talk Errors Fix
Final Analysis
Tool
Primetime
Formality
Modelsim
Nc-sim
Mgcomet
Voltagestorm
Patform
Se2gds
Celtic
Silicon Ensemble
Signalstorm
Supplier
Synopsys
Synopsys
Mentor
Cadence
Atmel
Cadence
Atmel
Atmel
Cadence
Cadence
Cadence
4261A–AERO–07/03
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부품번호상세설명 및 기능제조사
ATC18RHA

Rad. Hard 0.18 Um CMOS Cell-based ASIC for Space Use

ATMEL Corporation
ATMEL Corporation

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