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PDF MTB52N06V Data sheet ( Hoja de datos )
| Número de pieza | MTB52N06V | |
| Descripción | TMOS POWER FET 52 AMPERES 60 VOLTS | |
| Fabricantes | Motorola Semiconductors | |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MTB52N06V/D
™Designer's Data Sheet
TMOS V™
Power Field Effect Transistor
D2PAK for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
TMOS V is a new technology designed to achieve an on–resistance
area product about one–half that of standard MOSFETs. This new
technology more than doubles the present cell density of our 50
and 60 volt TMOS devices. Just as with our TMOS E–FET designs,
TMOS V is designed to withstand high energy in the avalanche and
commutation modes. Designed for low voltage, high speed
switching applications in power supplies, converters and power
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas
are critical and offer additional safety margin against unexpected
voltage transients.
New Features of TMOS V
• On–resistance Area Product about One–half that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
• Faster Switching than E–FET Predecessors
G
Features Common to TMOS V and TMOS E–FETs
• Avalanche Energy Specified
• IDSS and VDS(on) Specified at Elevated Temperature
• Static Parameters are the Same for both TMOS V and TMOS E–FET
• Surface Mount Package Available in 16 mm 13–inch/2500 Unit
Tape & Reel, Add T4 Suffix to Part Number
MTB52N06V
Motorola Preferred Device
TMOS POWER FET
52 AMPERES
60 VOLTS
RDS(on) = 0.022 OHM
TM
D
CASE 418B–02, Style 2
S D2PAK
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–Source Voltage
Drain–Gate Voltage (RGS = 1.0 MΩ)
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms)
VDSS 60 Vdc
VDGR 60 Vdc
VGS
± 20 Vdc
VGSM ± 25 Vpk
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
ID 52 Adc
ID 41
IDM 182 Apk
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TA = 25°C (1)
PD 188 Watts
1.25 W/°C
3.0 Watts
Operating and Storage Temperature Range
TJ, Tstg – 55 to 175 °C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 52 Apk, L = 0.3 mH, RG = 25 Ω)
EAS 406 mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient (1)
RθJC
RθJA
RθJA
0.8 °C/W
62.5
50
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
TL 260 °C
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET, Designer’s, and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 3
© MMoototororloa,laIncT.M19O96S Power MOSFET Transistor Device Data
1
1 page  
12
10
8
Q1
6
Q2
QT
VGS
4
2
Q3
0
VDS
0 20 40 60 80 100
QT, TOTAL CHARGE (nC)
36
33
30
27
24
21
18
15
12
ID = 52 A 9
TJ = 25°C 6
3
0
120 140
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
1000
VDD = 30 V
ID = 52 A
VGS = 10 V
TJ = 25°C
100
tr
tf
td(off)
10 td(on)
MTB52N06V
1
1 10 100
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
55
50
VGS = 0 V
TJ = 25°C
45
40
35
30
25
20
15
10
5
0
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance–General
Data and Its Use.”
Switching between the off–state and the on–state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the transition
time (tr,tf) do not exceed 10 µs. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) – TC)/(RθJC).
A Power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E–FETs can withstand the stress of
drain–to–source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.
Motorola TMOS Power MOSFET Transistor Device Data
5
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| PDF Descargar | [ Datasheet MTB52N06V.PDF ] | |
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