Datasheet.kr   

MTB4N80E1 데이터시트 PDF




Motorola Semiconductors에서 제조한 전자 부품 MTB4N80E1은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 MTB4N80E1 자료 제공

부품번호 MTB4N80E1 기능
기능 TMOS POWER FET 4.0 AMPERES 800 VOLTS
제조업체 Motorola Semiconductors
로고 Motorola Semiconductors 로고


MTB4N80E1 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.



전체 8 페이지수

미리보기를 사용할 수 없습니다

MTB4N80E1 데이터시트, 핀배열, 회로
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Product Preview
TMOS E-FET.
High Energy Power FET
D2PAK-SL Straight Lead
N–Channel Enhancement–Mode Silicon Gate
This high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltage–blocking capability without
degrading performance over time. In addition, this advanced TMOS
E–FET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
drain–to–source diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
Robust High Voltage Termination
Avalanche Energy Specified
Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Short Heatsink Tab Manufactured — Not Sheared
Specially Designed Leadframe for Maximum Power Dissipation
G
®
D
S
Order this document
by MTB4N80E1/D
MTB4N80E1
Motorola Preferred Device
TMOS POWER FET
4.0 AMPERES
800 VOLTS
RDS(on) = 3.0 OHM
CASE 418C–01, Style 2
D2PAK–SL
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Drain–Source Voltage
VDSS
800
Drain–Gate Voltage (RGS = 1.0 M)
VDGR
800
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp 10 ms)
VGS
VGSM
± 20
± 40
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp 10 µs)
ID 4.0
ID 2.9
IDM 12
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TA = 25°C, when mounted with the minimum recommended pad size
PD 125
1.0
2.5
Operating and Storage Temperature Range
TJ, Tstg – 55 to 150
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 100 Vdc, VGS = 10 Vdc, IL = 8.0 Apk, L = 10 mH, RG = 25 )
EAS
320
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient, when mounted with the minimum recommended pad size
RθJC
RθJA
RθJA
1.0
62.5
50
Maximum Lead Temperature for Soldering Purposes, 1/8from case for 10 seconds
TL 260
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
E–FET is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Apk
Watts
W/°C
Watts
°C
mJ
°C/W
°C
©MMoottoororolal,aInTc.M19O9S7 Power MOSFET Transistor Device Data
1




MTB4N80E1 pdf, 반도체, 판매, 대치품
MTB4N80E1
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when cal-
culating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.
2800
Ciss VDS = 0 V
2400
VGS = 0 V
TJ = 25°C
2000
1600
Crss
1200
Ciss
800
400
0
10
Crss
50
5
VGS VDS
Coss
10 15 20
25
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7a. Capacitance Variation
10000
VGS = 0 V
1000
TJ = 25°C
Ciss
100
Coss
10 Crss
1
10 100 1000
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7b. High Voltage Capacitance
Variation
4 Motorola TMOS Power MOSFET Transistor Device Data

4페이지










MTB4N80E1 전자부품, 판매, 대치품
PACKAGE DIMENSIONS
MTB4N80E1
W
–T–
SEATING
PLANE
F
C
–B–
4
123
SK
G
D 3 PL
0.13 (0.005) M T B M
E
V
A
J
H
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
INCHES
DIM MIN MAX
A 0.340 0.380
B 0.380 0.405
C 0.160 0.190
D 0.020 0.035
E 0.045 0.055
F 0.039 REF
G 0.100 BSC
H 0.080 0.110
J 0.018 0.025
K 0.280 0.360
S 0.276 REF
V 0.045 0.055
W 0.423 0.462
MILLIMETERS
MIN MAX
8.64 9.65
9.65 10.29
4.06 4.83
0.51 0.89
1.14 1.40
1.00 REF
2.54 BSC
2.03 2.79
0.46 0.64
7.11 9.14
7.00 REF
1.14 1.40
10.75 11.75
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
CASE 418C–01
ISSUE O
Motorola TMOS Power MOSFET Transistor Device Data
7

7페이지


구       성 총 8 페이지수
다운로드[ MTB4N80E1.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
MTB4N80E

TMOS POWER FET 4.0 AMPERES 800 VOLTS

Motorola Semiconductors
Motorola Semiconductors
MTB4N80E1

TMOS POWER FET 4.0 AMPERES 800 VOLTS

Motorola Semiconductors
Motorola Semiconductors

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵