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PDF 54SXxx Data sheet ( Hoja de datos )
| Número de pieza | 54SXxx | |
| Descripción | FPGAs | |
| Fabricantes | Actel | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 54SXxx (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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v3.1
54SX Family FPGAs
Leading Edge Performance
• 320 MHz Internal Performance
• 3.7 ns Clock-to-Out (Pin-to-Pin)
• 0.1 ns Input Set-Up
• 0.25 ns Clock Skew
Specifications
• 12,000 to 48,000 System Gates
• Up to 249 User-Programmable I/O Pins
• Up to 1080 Flip-Flops
• 0.35µ CMOS
SX Product Profile
Capacity
Typical Gates
System Gates
Logic Modules
Combinatorial Cells
Register Cells (Dedicated Flip-Flops)
Maximum User I/Os
Clocks
JTAG
PCI
Clock-to-Out
Input Set-Up (External)
Speed Grades
Temperature Grades
Packages (by pin count)
PLCC
PQFP
VQFP
TQFP
PBGA
FBGA
A54SX08
8,000
12,000
768
512
256
130
3
Yes
—
3.7 ns
0.8 ns
Std, –1, –2, –3
C, I, M
84
208
100
144, 176
—
144
Features
• 66 MHz PCI
• CPLD and FPGA Integration
• Single Chip Solution
• 100% Resource Utilization with 100% Pin Locking
• 3.3V Operation with 5.0V Input Tolerance
• Very Low Power Consumption
• Deterministic, User-Controllable Timing
• Unique In-System Diagnostic and Debug capability with
Silicon Explorer II
• Boundary Scan Testing in Compliance with IEEE Standard
1149.1 (JTAG)
• Secure Programming Technology Prevents Reverse
Engineering and Design Theft
A54SX16
16,000
24,000
1,452
924
528
175
3
Yes
—
3.9 ns
0.5 ns
Std, –1, –2, –3
C, I, M
—
208
100
176
—
—
A54SX16P
16,000
24,000
1,452
924
528
175
3
Yes
Yes
4.4 ns
0.5 ns
Std, –1, –2, –3
C, I, M
—
208
100
144, 176
—
—
A54SX32
32,000
48,000
2,880
1800
1,080
249
3
Yes
—
4.6 ns
0.1 ns
Std, –1, –2, –3
C, I, M
—
208
—
144, 176
313, 329
—
June 2003
© 2003 Actel Corporation
1
1 page  
54SX Family FPGAs
The C-cell implements a range of combinatorial functions
up to 5-inputs (Figure 3). Inclusion of the DB input and its
associated inverter function dramatically increases the
number of combinatorial functions that can be
implemented in a single module from 800 options in
previous architectures to more than 4,000 in the SX
architecture. An example of the improved flexibility
enabled by the inversion capability is the ability to integrate
a 3-input exclusive-OR function into a single C-cell. This
facilitates construction of 9-bit parity-tree functions with 2
ns propagation delays. At the same time, the C-cell
structure is extremely synthesis friendly, simplifying the
overall design and reducing synthesis time.
Routed
Data Input S1
S0
Direct
Connect
Input
PSETB
DQ
Y
Figure 2 • R-Cell
HCLK
CLKA,
CLKB,
Internal Logic
CKS
D0
D1
D2
D3
CKP
CLRB
Y
Sa Sb
DB
A0 B0
A1 B1
Figure 3 • C-Cell
Chip Architecture
The SX family’s chip architecture provides a unique
approach to module organization and chip routing that
delivers the best register/logic mix for a wide variety of new
and emerging applications.
Module Organization
Actel has arranged all C-cell and R-cell logic modules into
horizontal banks called Clusters. There are two types of
Clusters: Type 1 contains two C-cells and one R-cell, while
Type 2 contains one C-cell and two R-cells.
To increase design efficiency and device performance, Actel
has further organized these modules into SuperClusters
(Figure 4 on page 6). SuperCluster 1 is a two-wide grouping
of Type 1 clusters. SuperCluster 2 is a two-wide group
containing one Type 1 cluster and one Type 2 cluster. SX
devices feature more SuperCluster 1 modules than
SuperCluster 2 modules because designers typically require
significantly more combinatorial logic than flip-flops.
v3.1
5
5 Page 
54SX Family FPGAs
PCI Compliance for the 54SX Family
The 54SX family supports 3.3V and 5V PCI and is compliant with the PCI Local Bus Specification Rev. 2.1.
A54SX16P DC Specifications (5.0V PCI Operation)
Symbol Parameter
Condition
Min.
Max. Units
VCCA
Supply Voltage for Array
3.0 3.6 V
VCCR
Supply Voltage required for Internal Biasing
4.75 5.25
V
VCCI
VIH
VIL
Supply Voltage for IOs
Input High Voltage1
Input Low Voltage1
4.75
2.0
–0.5
5.25
VCC + 0.5
0.8
V
V
V
IIH Input High Leakage Current
VIN = 2.7
70 µA
IIL Input Low Leakage Current
VIN = 0.5
–70 µA
VOH Output High Voltage
VOL Output Low Voltage2
CIN Input Pin Capacitance3
IOUT = –2 mA
IOUT = 3 mA, 6 mA
2.4 V
0.55 V
10 pF
CCLK
CIDSEL
CLK Pin Capacitance
IDSEL Pin Capacitance4
5 12 pF
8 pF
Notes:
1. Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs.
2. Signals without pull-up resistors must have 3 mA low output current. Signals requiring pull up must have 6 mA; the latter include,
FRAME#, IRDY#, TRDY#, DEVSEL#, STOP#, SERR#, PERR#, LOCK#, and, when used AD[63::32], C/BE[7::4]#, PAR64, REQ64#, and ACK64#.
3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK).
4. Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx].
v3.1
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 54SXxx.PDF ] | |
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