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Datasheet 54SXXX Equivalent ( PDF ) |
| N.º | Número de pieza | Descripción | Fabricantes | Category |
| 1 | 54SXxx | FPGAs v3.1
54SX Family FPGAs
Le a di ng E dg e P er f or m a nc e F ea t u r es
• 320 MHz Internal Performance • 3.7 ns Clock-to-Out (Pin-to-Pin) • 0.1 ns Input Set-Up • 0.25 ns Clock Skew
Sp e ci f ic at ion s
• 66 MHz PCI • CPLD and FPGA Integration • Single Chip Solution • 100% Resou |  Actel | data |
| 2 | 54SXxx | General Purpose SDRAM Controller v2.0
General-Purpose SDRAM Controller
SD R A M Co n t r o l l er Fu nc t i o na l D es cr i p t i o n
The general-purpose SDRAM controller is designed to provide simplified control of many different sizes of SDRAMs. The controller architecture provides control for data bursts by linearly increment | Actel | controller |
| 3 | 54SXxxA | SX-A Family FPGAs v5.1
SX-A Family FPGAs
Leading-Edge Performance
• • 250 MHz System Performance 350 MHz Internal Performance • • • • • • • • • •
™
Specifications
• • • • 12,000 to 108,000 Available System Gates Up to 360 User-Programmable I/O Pins Up to 2,012 Dedicated Flip-Flops | Actel | data |
54S Datasheet ( Hoja de datos ) - resultados coincidentes |
| N.º | Número de pieza | Descripción | Fabricantes | Catagory |
| 1 | 54S04 | HEX INVERTING GATES DM54S04 DM74S04 Hex Inverting Gates
DM54S04 DM74S04 Hex Inverting Gates
General Description
This device contains six independent gates each of which performs the logic INVERT function
Connection Diagram
Dual-In-Line Package
June 1989
TL F 6442 – 1
Order Number DM54S04J DM54S04W DM74S04M or DM74  National Semiconductor gate | | |
| 2 | 54S08 | Quad 2-Input AND Gates DM54S08 DM74S08 Quad 2-Input AND Gates
DM54S08 DM74S08 Quad 2-Input AND Gates
General Description
This device contains four independent gates each of which performs the logic AND function
Connection Diagram
Dual-In-Line Package
June 1989
Function Table
Order Number DM54S08J DM54S08W or DM74S0 National Semiconductor gate | | |
| 3 | 54S08 | Quadruple 2-Input Positive-AND Gates Texas Instruments gate | | |
| 4 | 54S10 | STTL type three 3-input NAND gate 54S10/74S10 STTL 型三 3 输入与非门 典型参数： tpd=3ns Pd=19mW/每门 线路图（1/3）
逻辑符号
逻辑式： 外引线排列图： 逻辑表：
输入 B H × L × 输出 Y L H H H
A H L × ×
C H × × L
推荐工作条件
74Ⅱ 符号 Vcc VIH VIL IOH IOL TA 参数名称 最小  TW gate | | |
| 5 | 54S112 | STTL double-J-K flip-flop 54S112/74S112 STTL 型双 J－K 触发器 （负沿触发、 带清零和预置） 典型参数： f 工作频率=125MHz Pd=75mW 外引线排列图
逻辑图
功能表
输 预置
PRE
入 时钟
输 K × × × L L H H ×
出
清除
CLR
CLK
× × × ↓ ↓ ↓ ↓ H
J × × × L H L H ×
H=� TW flip-flop | | |
| 6 | 54S138 | STTL type 3-to-8 line decoder / demodulator 54S138/74S138 STTL 型 3 线-8 线译码器/解调器 特点：
·专为高速存贮译码和数据传输系 统而设计 ·有三个赋能输入,简化了级联与/ 或数据接收 ·高性能的肖特基钳位技术
逻辑图
典型参数： tpd=8ns(使能) tpd=7ns(选择) Pd=245mW
外引线排  BDTIC data | | |
| 7 | 54S15 | STTL type three 3-input AND gate 54S15/74S15 STTL 型三 3 输入与门(OC) 典型参数： tpd=5.5ns Pd=29mW/每门 线路图（1/3）
逻辑符号：
逻辑式： 逻辑表：
A H L × × 输入 B H × L × C H × × L 输出 Y H L L L
外引线排列图：
推荐工作条件
74Ⅱ 符号 Vcc VIH VIL VOH IOL TA 参数名称 � TW gate | |
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