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부품번호 | A54SXxxA 기능 |
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기능 | SX-A Family FPGAs | ||
제조업체 | Actel | ||
로고 | |||
SX-A Family FPGAs
v5.1
™
Leading-Edge Performance
• 250 MHz System Performance
• 350 MHz Internal Performance
Specifications
• 12,000 to 108,000 Available System Gates
• Up to 360 User-Programmable I/O Pins
• Up to 2,012 Dedicated Flip-Flops
• 0.22 µ / 0.25 µ CMOS Process Technology
Features
• Hot-Swap Compliant I/Os
• Power-Up/Down Friendly (No Sequencing Required
for Supply Voltages)
• 66 MHz PCI Compliant
• Nonvolatile, Single-Chip Solution
• Configurable I/O Support for 3.3 V / 5 V PCI, 5 V
TTL, 3.3 V LVTTL, 2.5 V LVCMOS2
• 2.5 V, 3.3 V, and 5 V Mixed-Voltage Operation with
5 V Input Tolerance and 5 V Drive Strength
• Devices Support Multiple Temperature Grades
• Configurable Weak-Resistor Pull-Up or Pull-Down
for I/O at Power-Up
• Individual Output Slew Rate Control
• Up to 100% Resource Utilization and 100% Pin
Locking
• Deterministic, User-Controllable Timing
• Unique In-System Diagnostic and Verification
Capability with Silicon Explorer II
• Boundary-Scan Testing in Compliance with IEEE
Standard 1149.1 (JTAG)
• Actel Secure Programming Technology with
FuseLock™ Prevents Reverse Engineering and
Design Theft
Table 1 • SX-A Product Profile
Device
A54SX08A
A54SX16A
A54SX32A
Capacity
Typical Gates
System Gates
8,000
12,000
16,000
24,000
32,000
48,000
Logic Modules
Combinatorial Cells
Dedicated Flip-Flops
Maximum Flip-Flops
768
512
256
512*
1,452
924
528
990
2,880
1,800
1,080
1,980
Maximum User I/Os
130 180 249
Global Clocks
333
Quadrant Clocks
000
Boundary Scan Testing
Yes Yes Yes
3.3 V / 5 V PCI
Yes Yes Yes
Input Set-Up (External)
0 ns 0 ns 0 ns
Speed Grades
–F, Std, –1, –2
–F, Std, –1, –2, –3 –F, Std, –1, –2, –3
Temperature Grades
C, I, A, M
C, I, A, M
C, I, A, M
Package (by pin count)
PQFP
TQFP
PBGA
FBGA
CQFP
208
100, 144
–
144
–
208
100, 144
–
144, 256
–
208
100, 144, 176
329
144, 256, 484
208, 256
Note: *A maximum of 512 registers is possible if all 512 C cells are used to build an additional 256 registers
A54SX72A
72,000
108,000
6,036
4,024
2,012
4,024
360
3
4
Yes
Yes
0 ns
–F, Std, –1, –2, –3
C, I, A, M
208
–
–
256, 484
208, 256
February 2005
© 2005 Actel Corporation
i
See the Actel website for the latest version of the datasheet.
SX-A Family FPGAs
Table of Contents
General Description
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
SX-A Family Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
Detailed Specifications
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Typical SX-A Standby Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
PCI Compliance for the SX-A Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
SX-A Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
Sample Path Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
Output Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
AC Test Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
Input Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
C-Cell Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
Cell Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Temperature and Voltage Derating Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
Package Pin Assignments
208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
100-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
144-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
176-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
329-Pin PBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
144-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
256-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
484-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26
iv v5.1
4페이지 General Description
SX-A Family FPGAs
Introduction
The Actel SX-A family of FPGAs offers a cost-effective,
single-chip solution for low-power, high-performance
designs. Fabricated on 0.22 µm / 0.25 µm CMOS
antifuse technology and with the support of 2.5 V,
3.3 V and 5 V I/Os, the SX-A is a versatile platform to
integrate designs while significantly reducing time-
to-market.
SX-A Family Architecture
The SX-A family’s device architecture provides a unique
approach to module organization and chip routing that
satisfies performance requirements and delivers the most
optimal register/logic mix for a wide variety of
applications.
Interconnection between these logic modules is achieved
using Actel’s patented metal-to-metal programmable
antifuse interconnect elements (Figure 1-1). The
antifuses are normally open circuit and, when
programmed, form a permanent low-impedance
connection.
Routing Tracks
Metal 4
Metal 3
Metal 2
Amorphous Silicon/
Dielectric Antifuse
Tungsten Plug Via
Tungsten Plug Via
Tungsten Plug Contact
Metal 1
Silicon Substrate
Note: The A54SX72A device has four layers of metal with the antifuse between Metal 3 and Metal 4. The A54SX08A, A54SX16A, and
A54SX32A devices have three layers of metal with the antifuse between Metal 2 and Metal 3.
Figure 1-1 • SX-A Family Interconnect Elements
v5.1
1-1
7페이지 | |||
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부품번호 | 상세설명 및 기능 | 제조사 |
A54SXxx | FPGAs | Actel |
A54SXxxA | SX-A Family FPGAs | Actel |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |