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HIP6603B 데이터시트 PDF




Intersil Corporation에서 제조한 전자 부품 HIP6603B은 전자 산업 및 응용 분야에서
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부품번호 HIP6603B 기능
기능 (HIP6601B / HIP6603B / HIP6604B) Synchronous Rectified Buck MOSFET Drivers
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HIP6603B 데이터시트, 핀배열, 회로
HIP6601B, HIP6603B, HIP6604B
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December 10, 2015
FN9072.9
Synchronous Rectified Buck
MOSFET Drivers
The HIP6601B, HIP6603B and HIP6604B are high-
frequency, dual MOSFET drivers specifically designed to
drive two power N-Channel MOSFETs in a synchronous
rectified buck converter topology. These drivers combined
with a HIP63xx or the ISL65xx series of Multi-Phase Buck
PWM controllers and MOSFETs form a complete core-
voltage regulator solution for advanced microprocessors.
The HIP6601B drives the lower gate in a synchronous
rectifier to 12V, while the upper gate can be independently
driven over a range from 5V to 12V. The HIP6603B drives
both upper and lower gates over a range of 5V to 12V. This
drive-voltage flexibility provides the advantage of optimizing
applications involving trade-offs between switching losses
and conduction losses. The HIP6604B can be configured as
either a HIP6601B or a HIP6603B.
The output drivers in the HIP6601B, HIP6603B and
HIP6604B have the capacity to efficiently switch power
MOSFETs at frequencies up to 2MHz. Each driver is capable
of driving a 3000pF load with a 30ns propagation delay and
50ns transition time. These products implement
bootstrapping on the upper gate with only an external
capacitor required. This reduces implementation complexity
and allows the use of higher performance, cost effective,
N-Channel MOSFETs. Adaptive shoot-through protection is
integrated to prevent both MOSFETs from conducting
simultaneously.
Features
• Drives Two N-Channel MOSFETs
• Adaptive Shoot-Through Protection
• Internal Bootstrap Device
• Supports High Switching Frequency
- Fast Output Rise Time
- Propagation Delay 30ns
• Small 8 Ld SOIC and EPSOIC and 16 Ld QFN Packages
• Dual Gate-Drive Voltages for Optimal Efficiency
• Three-State Input for Output Stage Shutdown
• Supply Undervoltage Protection
• QFN Package
- Compliant to JEDEC PUB95 MO-220 QFN—Quad Flat
No Leads—Product Outline.
- Near Chip-Scale Package Footprint; Improves PCB
Efficiency and Thinner in Profile.
• Pb-Free (RoHS Compliant)
Applications
• Core Voltage Supplies for Intel Pentium® III, AMD®
Athlon™ Microprocessors
• High Frequency Low Profile DC/DC Converters
• High Current Low Voltage DC/DC Converters
Related Literature
• Technical Brief TB363, Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark of Intersil Americas LLC
Copyright © Intersil Americas LLC 2002-2005, 2012, 2015. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.




HIP6603B pdf, 반도체, 판매, 대치품
HIP6601B, HIP6603B, HIP6604B
Typical Application: 3-Channel Converter Using HIP6301 and HIP6601B Gate Drivers
+5V
PVCC
VCC
BOOT
UGATE
DRIVE PHASE
PWM HIP6601B
LGATE
+12V
PGOOD
VID
+5V
VFB
COMP
VCC
VSEN
PWM1
PWM2
PWM3
MAIN
CONTROL
HIP6301
ISEN1
ISEN2
FS ISEN3
GND
+5V
BOOT
PVCC
VCC
UGATE
PWM DRIVE PHASE
HIP6601B
LGATE
+12V
+5V
BOOT
VCC
PWM
PVCC
UGATE
DRIVE PHASE
HIP6601B
LGATE
+12V
+VCORE
4 FN9072.9
December 10, 2015

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HIP6603B 전자부품, 판매, 대치품
HIP6601B, HIP6603B, HIP6604B
Functional Pin Description
UGATE (Pin 1), (Pin 16 QFN)
Upper gate drive output. Connect to gate of high-side power
N-Channel MOSFET.
BOOT (Pin 2), (Pin 2 QFN)
Floating bootstrap supply pin for the upper gate drive.
Connect a bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to
turn on the upper MOSFET. A resistor in series with boot
capacitor is required in certain applications to reduce ringing
on the BOOT pin. See “Internal Bootstrap Device” on page 8
for guidance in choosing the appropriate capacitor and
resistor values.
PWM (Pin 3), (Pin 3 QFN)
The PWM signal is the control input for the driver. The PWM
signal can enter three distinct states during operation, see the
“Three-State PWM Input” on page 8 for further details. Connect
this pin to the PWM output of the controller.
GND (Pin 4), (Pin 4 QFN)
Bias and reference ground. All signals are referenced to
this node.
PGND (Pin 5 QFN Package Only)
This pin is the power ground return for the lower gate driver.
LGATE (Pin 5), (Pin 7 QFN)
Lower gate drive output. Connect to gate of the low-side
power N-Channel MOSFET.
VCC (Pin 6), (Pin 9 QFN)
Connect this pin to a +12V bias supply. Place a high quality
bypass capacitor from this pin to GND.
LVCC (Pin 10 QFN Package Only)
Timing Diagram
Lower gate driver supply voltage.
PVCC (Pin 7), (Pin 11 QFN)
For the HIP6601B and the HIP6604B, this pin supplies the
upper gate drive bias. Connect this pin from +12V down to +5V.
For the HIP6603B, this pin supplies both the upper and
lower gate drive bias. Connect this pin to either +12V or +5V.
PHASE (Pin 8), (Pin 14 QFN)
Connect this pin to the source of the upper MOSFET and the
drain of the lower MOSFET. The PHASE voltage is
monitored for adaptive shoot-through protection. This pin
also provides a return path for the upper gate drive.
Description
Operation
Designed for versatility and speed, the HIP6601B, HIP6603B
and HIP6604B dual MOSFET drivers control both high-side
and low-side N-Channel FETs from one externally provided
PWM signal.
The upper and lower gates are held low until the driver is
initialized. Once the VCC voltage surpasses the VCC Rising
Threshold (See “Electrical Specifications” on page 5), the
PWM signal takes control of gate transitions. A rising edge
on PWM initiates the turn-off of the lower MOSFET (see
“Timing Diagram” on page 7). After a short propagation
delay [tPDLLGATE], the lower gate begins to fall. Typical fall
times [tFLGATE] are provided in the “Electrical Specifications”
on page 5. Adaptive shoot-through circuitry monitors the
LGATE voltage and determines the upper gate delay time
[tPDHUGATE] based on how quickly the LGATE voltage
drops below 2.2V. This prevents both the lower and upper
MOSFETs from conducting simultaneously or shoot-through.
Once this delay period is complete the upper gate drive
begins to rise [tRUGATE] and the upper MOSFET turns on.
PWM
tPDHUGATE
UGATE
LGATE
tRUGATE
tPDLUGATE
tFUGATE
tPDLLGATE
tFLGATE
7
tPDHLGATE
tRLGATE
FN9072.9
December 10, 2015

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