|
|
PDF IDT70V9289L Data sheet ( Hoja de datos )
| Número de pieza | IDT70V9289L | |
| Descripción | HIGH-SPEED 3.3V 64K x 16 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de IDT70V9289L (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
|
No Preview Available !
HIGH-SPEED 3.3V 64K x 16
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
PRELIMINARY
IDT70V9289L
Features:
x True Dual-Ported memory cells which allow simultaneous
access of the same memory location
x High-speed clock to data access
– Commercial: 7.5/9/12ns (max.)
x Low-power operation
– IDT70V9289L
Active: 500mW (typ.)
Standby: 1.5mW (typ.)
x Flow-Through or Pipelined output mode on either port via
the FT/PIPE pins
x Counter enable and reset features
x Dual chip enables allow for depth expansion without
additional logic
x Full synchronous operation on both ports
– 4ns setup to clock and 0ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 7.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 12ns cycle time, 83MHz operation in Pipelined output mode
x Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
x LVTTL- compatible, single 3.3V (±0.3V) power supply
x Industrial temperature range (–40°C to +85°C) is
available for selected speeds
x Available in a 128-pin Thin Quad Flatpack (TQFP)
Functional Block Diagram
R/WL
UBL
CE0L
CE1L
LBL
OEL
1
0
0/1
FT/PIPEL
I/O8L-I/O15L
I/O0L-I/O7L
A15L
A0L
CLKL
ADSL
CNTENL
CNTRSTL
0/1
1b 0b
b
a 1a 0a
Counter/
Address
Reg.
I/O
Control
I/O
Control
MEMORY
ARRAY
R/WR
UBR
CE0R
1
0
CE1R
0/1
LBR
OER
0a 1a
a
b0b 1b
0/1
Counter/
Address
Reg.
FT/PIPER
I/O8R-I/O15R
I/O0R-I/O7R
A15R
A0R
CLKR
ADSR
CNTENR
CNTRSTR
4855 drw 01
©2000 Integrated Device Technology, Inc.
1
JUNE 2000
DSC-4855/1
1 page  
IDT70V9289L
High-Speed 64K x 16 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 3.3V ± 0.3V)
70V9289L
Symbol
Parameter
Test Conditions
Min. Max. Unit
|ILI| Input Leakage Current(1)
VCC = 3.6V, VIN = 0V to VCC
___ 5 µ A
|ILO| Output Leakage Current
CE = VIH or CE1 = VIL, VOUT = 0V to VCC
___ 5 µ A
VOL Output Low Voltage
IOL = +4mA
___ 0.4 V
VOH Output High Voltage
IOH = -4mA
2.4 ___ V
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
4855 tbl 08
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range(3,6) (VCC = 3.3V ± 0.3V)
70V9289L7
Com'l Only
70V9289L9
Com'l Only
70V9289L12
Com'l Only
Symbol
Parameter
Test Condition
Version
Typ.(4) Max. Typ.(4) Max. Typ.(4) Max. Unit
ICC Dynamic Operating CEL and CER= VIL,
Current (Both
Outputs Disabled,
Ports Active)
f = fMAX(1)
COM'L L 200 310 180 260 150 230 mA
IND L ____ ____ ____ ____ ____ ____
ISB1 Standby Current CEL = CER = VIH
(Both Ports - TTL
Level Inputs)
f = fMAX(1)
COM'L L 65
IND L ____
130 50
____ ____
100 40
____ ____
80 mA
____
ISB2 Standby
Current (One
Port - TTL
Level Inputs)
CE"A" = VIL and
CE"B" = VIH(5)
Active Port Outputs
Disabled, f=fMAX(1)
COM'L L 140 245 110 190 100 175 mA
IND L ____ ____ ____ ____ ____ ____
ISB3 Full Standby
Current (Both
Ports - CMOS
Level Inputs)
Both Ports CEL and
CER > VCC - 0.2V,
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(2)
COM'L L 0.4 3 0.4 3 0.4 3 mA
IND L ____ ____ ____ ____ ____ ____
ISB4 Full Standby
Current (One
Port - CMOS
Level Inputs)
CE"A" < 0.2V and
COM'L L 130 235 100 180 90 165 mA
CE"B" > VCC - 0.2V(5)
VIN > VCC - 0.2V or
IND L ____ ____ ____ ____ ____ ____
VIN < 0.2V, Active Port,
Outputs Disabled , f = fMAX(1)
NOTES:
4855 tbl 09
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. Vcc = 3.3V, TA = 25°C for Typ, and are not production tested. ICC DC(f=0) = 90mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V
CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V
"X" represents "L" for left port or "R" for right port.
6. Industrial temperature: for specific speeds, packages and powers contact your sales office.
6.452
5 Page 
IDT70V9289L
High-Speed 64K x 16 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(3)
tCYC1
tCH1
tCL1
CLK
CE0
CE1
UB, LB
R/W
tSC tHC
tSB tHB
tSW tHW
tSW tHW
(4)
ADDRESS
An
tSA tHA
An +1
DATAIN
DATAOUT
(2)
tCD1
tCD1
Qn
READ
tDC
An + 2
An + 2
An + 3
An + 4
tSD tHD
Dn + 2
Qn + 1
tCKHZ (1)
NOP (5)
WRITE
tCD1
tCD1
Qn + 3
tCKLZ(1)
tDC
READ
4855 drw 12
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(3)
tCYC1
tCH1
tCL1
CLK
CE0
CE1
UB, LB
R/W
tSC tHC
tSB tHB
tSW tHW
tSW tHW
ADDRESS(4)
DATAIN
DATAOUT
An
tSA tHA
tCD1
(2)
An +1
An + 2
tSD tHD
Dn + 2
tDC
Qn
tOHZ (1)
An + 3
Dn + 3
An + 4
An + 5
tOE
tCD1
(1)
tCKLZ
tCD1
Qn + 4
tDC
OE
READ
WRITE
READ
4855 drw 13
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.1412
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet IDT70V9289L.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| IDT70V9289 | HIGH-SPEED 3.3V 64K x18/x16 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM |  IDT |
| IDT70V9289L | HIGH-SPEED 3.3V 64K x18/x16 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM | IDT |
| IDT70V9289L | HIGH-SPEED 3.3V 64K x 16 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM | Integrated Device Technology |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |