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PDF CY28409 Data sheet ( Hoja de datos )
| Número de pieza | CY28409 | |
| Descripción | Clock Synthesizer with Differential SRC and CPU Outputs | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY28409
Clock Synthesizer with Differential SRC and CPU Outputs
Features
• Supports Intel Pentium 4-type CPUs
• Selectable CPU frequencies
• 3.3V power supply
• Ten copies of PCI clocks
• Five copies of 3V66 with one optional VCH
• Two copies 48-MHz USB clocks
• Three differential CPU clock pairs
• One differential SRC clock
• I2C support with readback capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
EMI reduction
• 56-pin SSOP and TSSOP packages
CPU
SRC
3V66
PCI
REF
48M
x3 x1
x 5 x 10 x 2 x 2
Block Diagram
XIN
XOUT
CPU_STP#
PCI_STP#
FS_[A:B]
VTT_PWRGD#
IREF
XTAL
OSC
PLL Ref Freq
PLL1
Divider
Network
PLL2
2
PD#
SDATA
SCLK
I2C
Logic
Pin Configuration[1]
VDD_REF
REF0:1
VDD_CPU
CPUT[0:2], CPUC[0:2]
VDD_SRC
SRCT, SRCC
VDD_3V66
3V66_[0:3]
VDD_PCI
PCIF[0:2]
PCI[0:6]
3V66_4/VCH
VDD_48MHz
DOT_48
USB_48
REF_0
REF_1
VDD_REF
XIN
XOUT
VSS_REF
PCIF0
PCIF1
PCIF2
VDD_PCI
VSS_PCI
PCI0
PCI1
PCI2
PCI3
VDD_PCI
VSS_PCI
PCI4
PCI5
PCI6
PD#
3V66_0
3V66_1
VDD_3V66
VSS_3V66
3V66_2
3V66_3
SCLK
1 56
2 55
3 54
4 53
5 52
6 51
7 50
8 49
9 48
10 47
11 46
12 45
13 44
14 43
15 42
16 41
17 40
18 39
19 38
20 37
21 36
22 35
23 34
24 33
25 32
26 31
27 30
28 29
56 SSOP/TSSOP
FS_B
VDD_A
VSS_A
VSS_IREF
IREF
FS_A
CPU_STP#
PCI_STP#
VDD_CPU
CPUT2
CPUC2
VSS_CPU
CPUT1
CPUC1
VDD_CPU
CPUT0
CPUC0
VSS_SRC
SRCT
SRCC
VDD_SRC
VTT_PWRGD#
VDD_48
VSS_48
DOT_48
USB_48
SDATA
3V66_4/VCH
Note:
1. Signals marked with [*] and [**] have internal pull-up and pull-down resistors, respectively.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07445 Rev. *B
Revised August 26, 2003
1 page  
Byte 0:Control Register 0 (continued)
Bit @Pup
Name
3 Externally PCI_STP#
Selected
2 Externally CPU_STP#
Selected
1 Externally FS_B
Selected
0 Externally FS_A
Selected
Byte 1: Control Register 1
Bit @Pup
Name
7 0 SRCT, SRCC
6 1 SRCT, SRCC
5 1 Reserved
4 1 Reserved
3 1 Reserved
2 1 CPUT2, CPUC2
1 1 CPUT1, CPUC1
0 1 CPUT0, CPUC0
Byte 2: Control Register 2
Bit @Pup
Name
7 0 SRCT, SRCC
6 0 SRCT, SRCC
5 0 CPUT2, CPUC2
4 0 CPUT1, CPUC1
3 0 CPUT0, CPUC0
2 0 CPUT2, CPUC2
1 0 CPUT1, CPUC1
0 0 CPUT0, CPUC0
Byte 3: Control Register 3
Bit @Pup
Name
7 1 SW PCI STOP
6 1 PCI6
CY28409
Description
PCI_STP# reflects the current value of the external PCI_STP# pin.
0 =PCI_STP# pin is low.
CPU_STP# reflects the current value of the external CPU_STP# pin.
0 = CPU_STP# pin is low.
FS_B reflects the value of the FS_B pin sampled on power-up.
FS_A reflects the value of the FS_A pin sampled on power-up.
Description
Allows control of SRCT/C with assertion of PCI_STP# or SW PCI_STP
0 = Free Running, 1 = Stopped with PCI_STP#
SRCT/C Output Enable; 0 = Disabled (Hi-z), 1 = Enabled
Reserved, Set = 1
Reserved, Set = 1
Reserved, Set = 1
CPUT/C2 Output Enable; 0 = Disabled (Hi-z), 1 = Enabled
CPUT/C1 Output Enable; 0 = Disabled (Hi-z), 1 = Enabled
CPUT/C0 Output Enable; 0 = Disabled (Hi-z), 1 = Enabled
Description
SRCT/C Pwrdwn Drive Mode
0 = Driven during power-down, 1 = Three-state during power-down
SRCT/C Stop Drive Mode
0 = Driven during PCI_STP, 1 = Three-state during PCI_STP
CPUT/C2 Pwrdwn Drive Mode
0 = Driven during power-down, 1 = Three-state during power-down
CPUT/C1 Pwrdwn Drive Mode
0 = Driven during power ‘down, 1 = Three-state during power-down
CPUT/C0 Pwrdwn Drive Mode
0 = Driven during power-down, 1 = Three-state during power-down
CPUT/C2 stop Drive Mode
0 = Driven when stopped, 1 = Three-state when stopped
CPUT/C1 stop Drive Mode
0 = Driven when stopped, 1 = Three-state when stopped
CPUT/C0 stop Drive Mode
0 = Driven when stopped, 1 = Three-state when stopped
Description
SW PCI_STP Function
0= PCI_STP assert, 1= PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI,PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
PCI6 Output Enable
0 = Disabled, 1 = Enabled
Document #: 38-07445 Rev. *B
Page 5 of 18
5 Page 
PCI_STP# Assertion[2]
The PCI_STP# signal is an active LOW input used for
synchronous stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The set-up
time for capturing PCI_STP# going LOW is 10 ns (tSU). (See
Figure 7.) The PCIF clocks will not be affected by this pin if
their corresponding control bit in the SMBus register is set to
allow them to be free-running.
PCI_STP#
Tsu
PCI_F
PCI
SRC 100MHz
CY28409
Figure 7. PCI_STP# Assertion Waveform
PCI_STP# Deassertion
The deassertion of the PCI_STP# signal will cause all PCI and
stoppable PCIF clocks to resume running in a synchronous
manner within two PCI clock periods after PCI_STP# transi-
tions to a high level.
Tsu Tdrive_SRC
PCI_STP#
PCI_F
PCI
SRC 100MHz
Figure 8. PCI_STP# Deassertion Waveform
Note:
2. The PCI STOP function is controlled by two inputs. One is the device PCI_STP# pin number 34 and the other is SMBus byte 0 bit 3. These two inputs are logically
ANDed. If either the external pin or the internal SMBus register bit is set low then the stoppable PCI clocks will be stopped in a logic low state. Reading SMBus
Byte 0 Bit 3 will return a 0 value if either of these control bits are set LOW thereby indicating the device’s stoppable PCI clocks are not running.
Document #: 38-07445 Rev. *B
Page 11 of 18
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet CY28409.PDF ] | |
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