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PDF TEA1201TS Data sheet ( Hoja de datos )
| Número de pieza | TEA1201TS | |
| Descripción | 0.95 V starting basic power unit | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
TEA1201TS
0.95 V starting basic power unit
Product specification
2002 Jun 06
1 page  
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handbook, full pagewidth
LBI1 9
LBO
LX1
LX2
10
1
16
ILIM 5
LOW BATTERY
DETECTOR
TEA1201TS
SHDWN0
P-type
POWER FET
sense FET
START-UP
CIRCUIT
INTERNAL
SUPPLY
6
OUT1
7
FB1
3, 4
UPOUT/ DNIN
8
GND
N-type
POWER
FET
13
GND0
sense
FET
Vref
CURRENT LIMIT
COMPARATOR
CONTROL LOGIC
AND
MODE GEARBOX
TEMPERATURE
PROTECTION
13 MHz
OSCILLATOR
SYNC
GATE
TIME
COUNTER
DIGITAL CONTROLLER
14 2 15
SYNC/PWM SHDWN0 U/D
12
Vref
FB0
REFERENCE 11
VOLTAGE
Vref
MGW787
Fig.1 Block diagram.
5 Page 
Philips Semiconductors
0.95 V starting basic power unit
Product specification
TEA1201TS
12 CHARACTERISTICS
Tamb = −20 to +80 °C; all voltages are measured with respect to ground; positive currents flow into the IC; unless
otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
DC-to-DC converter
UPCONVERSION; PIN U/D = LOW
VI(up)
VO(up)
VI(start)
VO(uvlo)
input voltage
output voltage
start-up input voltage
undervoltage lockout voltage
DOWNCONVERSION; PIN U/D = HIGH
VI(dwn)
VO(dwn)
input voltage
output voltage
REGULATION
∆VO(wdw) output voltage window size as a function
of output voltage
IL < 10 mA
note 1
note 2
PWM mode
VI(start)
VO(uvlo)
0.93
2.0
−
−
0.96
2.2
5.50
5.50
1.00
2.4
V
V
V
V
VO(uvlo) −
1.30 −
5.50 V
5.50 V
1.5 2.0 2.5 %
CURRENT LEVELS
Iq(DCDC)
Ishdwn
Ilim(max)
∆Ilim
quiescent current at pin UPOUT/DNIN
current in shut-down mode
maximum current limit
current limit deviation
ILX(max)
maximum continuous current at pins LX1
and LX2
note 3
VLBI1 = VI(up) = 1.2 V
Ilim set to 1.0 A; note 4
upconversion
downconversion
Tamb = 80 °C
−
−
−
−12
−12
−
110 −
65 −
5−
− +12
− +12
− 1.0
µA
µA
A
%
%
A
POWER MOSFETS
RDSon(N) drain-to-source on-state resistance NFET Tj = 27 °C; IDS = 100 mA −
RDSon(P) drain-to-source on-state resistance PFET Tj = 27 °C; IDS = −100 mA −
EFFICIENCY
η efficiency upconversion
VO up to 3.3 V; see note 5
and Fig.9
VI = 1.2 V; IL = 100 mA −
VI = 2.4 V; IL = 10 mA −
TIMING
fsw
fi(sync)
tstart
switching frequency
synchronization clock input frequency
start-up time
PWM mode
note 6
480
6
−
DIGITAL INPUT LEVELS
VlL(n)
LOW-level input voltage on all digital pins
0
110 200
125 250
84 −
92 −
600 720
13 20
10 −
− 0.4
mΩ
mΩ
%
%
kHz
MHz
ms
V
2002 Jun 06
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet TEA1201TS.PDF ] | |
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