PDF ADE7756 Data sheet ( Hoja de datos )

Número de pieza	ADE7756
Descripción	Active Energy Metering IC with Serial Interface
Fabricantes	Analog Devices
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No Preview Available ! a Active Energy Metering IC with Serial Interface ADE7756* FEATURES High Accuracy, Supports IEC 687/1036 Less than 0.1% Error over a Dynamic Range of 1000 to 1 An On-Chip User Programmable Threshold for Line Voltage SAG Detection and PSU Supervisory The ADE7756 Supplies Sampled Waveform Data (20 Bits) and Active Energy (40 Bits) Digital Power, Phase and Input Offset Calibration An On-Chip Temperature Sensor (؎3؇C Typical after Calibration) An SPI-Compatible Serial Interface A Pulse Output with Programmable Frequency An Interrupt Request Pin (IRQ) and Status Register Provide Early Warning of Register Overflow and Other Conditions Proprietary ADCs and DSP Provide High Accuracy over Large Variations in Environmental Conditions and Time Reference 2.4 V ؎ 8% (20 ppm/؇C Typical) with External Overdrive Capability Single 5 V Supply, Low Power (25 mW Typical) GENERAL DESCRIPTION The ADE7756 is a high-accuracy electrical power measurement IC with a serial interface and a pulse output. The ADE7756 incorporates two second-order sigma-delta ADCs, reference circuitry, temperature sensor, and all the signal processing required to perform active power and energy measurement. The ADE7756 contains a sampled Waveform register and an Active Energy register capable of holding at least five seconds of accumulated power at full load. Data is read from the ADE7756 via the serial interface. The ADE7756 also provides a pulse output (CF) with a frequency that is proportional to the active power. In addition to real power information, the ADE7756 also provides system calibration features, i.e., channel offset correction, phase calibration, and power calibration. The part also incorporates a detection circuit for short duration low voltage variations or sags. The voltage threshold level and the duration (in number of half- line cycles) of the variation are user programmable. An open drain logic output (SAG) goes active low when a sag event occurs. A zero crossing output (ZX) produces an output that is synchro- nized to the zero crossing point of the line voltage. This output can be used to extract timing or frequency information from the line. The signal is also used internally to the chip in the calibration mode. This permits faster and more accurate calibration of the real power calculation. This signal is also useful for synchronization of relay switching with a voltage zero crossing, thus improving the relay life by reducing the risk of arcing. The interrupt request output is an open drain, active low logic output. The IRQ output will become active when the accumu- lated real power register is half-full and also when the register overflows. A status register indicates the nature of the interrupt. The ADE7756 is available in 20-lead DIP and 20-lead SSOP packages. V1P V1N V2P V2N FUNCTIONAL BLOCK DIAGRAM AVDD RESET DVDD DGND PGA ADC MULTIPLIER HPF1 MULTIPLIER LPF2 ADE7756 TEMP SENSOR ADC APGAIN[11:0] PHCAL[5:0] ⌽ APOS[11:0] DFC 2.4V 4k⍀ REFERENCE LPF1 ADE7756 REGISTERS AND SERIAL INTERFACE CFDIV[11:0] ZX SAG CF AGND REFIN/OUT DIN DOUT SCLK CS IRQ CLKIN CLKOUT *U.S. Patents 5,745,323; 5,760,617; 5,862,069; 5,872,469; other pending. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 1 page ADE7756 TIMING CHARACTERISTICS1, 2 (AVDD = DVDD = 5 V ؎ 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.579545 MHz XTAL, TMIN to TMAX = –40؇C to +85؇C, unless otherwise noted.) Parameter A, B Versions Unit Test Conditions/Comments Write Timing t1 t2 t3 t4 t5 t6 t7 t8 Read Timing t9 t10 t113 t124 t134 20 150 150 10 5 6.4 4 100 4 4 30 100 10 100 10 ns (min) ns (min) ns (min) ns (min) ns (min) µs (min) µs (min) ns (min) µs (min) µs (min) ns (min) ns (max) ns (min) ns (max) ns (min) CS falling edge to first SCLK falling edge. SCLK logic high pulsewidth. SCLK logic low pulsewidth. Valid Data Setup time before falling edge of SCLK. Data Hold time after SCLK falling edge. Minimum time between the end of data byte transfers. Minimum time between byte transfers during a serial write. CS Hold time after SCLK falling edge. Minimum time between read command (i.e., a write to Communication Register) and data read. Minimum time between data byte transfers during a multibyte read. Data access time after SCLK rising edge following a write to the Communications Register. Bus relinquish time after falling edge of SCLK. Bus relinquish time after rising edge of CS. NOTES 1Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns (10% to 90%) and timed from a voltage level of 1.6 V. 2See timing diagram below and Serial Interface section of this data sheet. 3Measured with the load circuit in Load Circuit for Timing Specifications and defined as the time required for the output to cross 0.8 V or 2.4 V. 4Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Load Circuit for Timing Specifications. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. Specifications subject to change without notice. 200␮A IOL TO OUTPUT PIN CL 50pF 1.6mA 2.1V IOH Figure 1. Load Circuit for Timing Specifications CS SCLK t1 DIN t8 t2 t3 t4 t5 1 0 0 A4 A3 A2 A1 A0 DB7 t6 t7 DB0 DB7 DB0 COMMAND BYTE MOST SIGNIFICANT BYTE Figure 2. Serial Write Timing LEAST SIGNIFICANT BYTE CS SCLK t1 t9 t10 t13 REV. 0 DIN DOUT 0 0 0 A4 A3 A2 A1 A0 t11 DB7 t11 DB0 COMMAND BYTE MOST SIGNIFICANT BYTE Figure 3. Serial Read Timing –5– DB7 t12 DB0 LEAST SIGNIFICANT BYTE 5 Page 40A TO 40mA 10␮F RB 1k⍀ RB 33nF 1k⍀ 33nF 110V 1k⍀ 33nF 1M⍀ 1k⍀ 33nF 10␮F 100nF VDD 100nF 100nF AVDD DVDD RESET DIN DOUT V1P U1 SCLK ADE7756 CS V1N CLKOUT V2N CLKIN IRQ 10␮F TO SPI BUS (USED ONLY FOR CALIBRATION) Y1 3.58MHz 22pF 22pF V2P SAG NOT CONNECTED ZX REFIN/OUT AGND CF DGND CT TURN RATIO = 1800:1 CHANNEL 2 GAIN = 4 GAIN(CH1) RB 1 15.8⍀ 2 7.5⍀ 4 4.0⍀ 8 2.0⍀ 16 1.0⍀ U3 TO FREQUENCY COUNTER PS2501-1 TPC 13. Test Circuit for Performance Curves 0.50 0.40 0.30 5.25V 0.20 0.10 0 5.0V –0.10 –0.20 4.75V –0.30 –0.40 –0.50 0.01 0.10 1.0 10.0 100.0 AMPS TPC 14. PSR with Internal Reference ADE7756 0.8 0.6 0.4 PF = 1 0.2 PF = 0.5 0 –0.2 –0.4 –0.6 45 50 55 60 65 70 75 FREQUENCY – Hz TPC 15. Error as a % of Reading over Frequency 0.50 0.40 0.30 0.20 0.10 0 5.25V 5.0V –0.10 –0.20 4.75V –0.30 –0.40 –0.50 0.01 0.10 1.0 AMPS 10.0 100.0 TPC 16. PSR with External Reference REV. 0 –11– 11 Page

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