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ADCMP565 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 ADCMP565은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 ADCMP565 자료 제공

부품번호 ADCMP565 기능
기능 Dual Ultrafast Voltage Comparator
제조업체 Analog Devices
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ADCMP565 데이터시트, 핀배열, 회로
FEATURES
300 ps propagation delay input to output
50 ps propagation delay dispersion
Differential ECL compatible outputs
Differential latch control
Robust input protection
Input common-mode range −2.0 V to +3.0 V
Input differential range ±5 V
Power supply sensitivity greater than 65 dB
200 ps minimum pulsewidth
5 GHz equivalent input rise time bandwidth
Typical output rise/fall of 160 ps
SPT 9689 replacement
APPLICATIONS
High speed instrumentation
Scope and logic analyzer front ends
Window comparators
High speed line receivers and signal restoration
Threshold detection
Peak detection
High speed triggers
Patient diagnostics
Disk drive read channel detection
Hand-held test instruments
Zero-crossing detectors
Clock drivers
Automatic test equipment
Dual Ultrafast
Voltage Comparator
ADCMP565
FUNCTIONAL BLOCK DIAGRAM
NONINVERTING
INPUT
INVERTING
INPUT
ADCMP565
Q OUTPUT
Q OUTPUT
LATCH ENABLE
INPUT
LATCH ENABLE
INPUT
Figure 1.
02820-0-001
GENERAL DESCRIPTION
The ADCMP565 is an ultrafast voltage comparator fabricated
on Analog Devices’ proprietary XFCB process. The device
features 300 ps propagation delay with less than 50 ps overdrive
dispersion. Overdrive dispersion, a particularly important
characteristic of high speed comparators, is a measure of the
difference in propagation delay under differing overdrive
conditions.
A fast, high precision differential input stage permits consis-
tent propagation delay with a wide variety of signals in the
common-mode range from −2.0 V to +3.0 V. Outputs are
complementary digital signals fully compatible with ECL 10 K
and 10 KH logic families. The outputs provide sufficient drive
current to directly drive transmission lines terminated in 50 Ω
to −2 V. A latch input is included, which permits tracking,
track-and-hold, or sample-and-hold modes of operation.
The ADCMP565 is available in a 20-lead PLCC package.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved.




ADCMP565 pdf, 반도체, 판매, 대치품
ADCMP565
Parameter
AC PERFORMANCE (continued)
Toggle Rate
Minimum Pulse Width
Unit to Unit Propagation Delay Skew
POWER SUPPLY
Positive Supply Current
Negative Supply Current
Positive Supply Voltage
Negative Supply Voltage
Power Dissipation
Power Dissipation
Power Supply Sensitivity—VCC
Power Supply Sensitivity—VEE
Symbol
PW
Condition
>50% output swing
∆tPD from 10 ns to
200 ps < ±50 ps
IVCC
IVEE
VCC
VEE
PSSVCC
PSSVEE
@ +5.0 V
@ −5.2 V
Dual
Dual
Dual, without load
Dual, with load
NOTE: Under no circumstances should the input voltages exceed the supply voltages.
Min Typ
5
200
±10
10
60
4.75
−4.96
370
13
70
5.0
−5.2
435
550
67
83
Max Unit
Gbps
ps
ps
18
80
5.25
−5.45
490
mA
mA
V
V
mW
mW
dB
dB
Rev. 0 | Page 4 of 16

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ADCMP565 전자부품, 판매, 대치품
Pin No.
18
19
20
Mnemonic
GND
QB
QB
ADCMP565
Function
Analog Ground
One of two complementary outputs for Channel B. QB will be at logic low if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the comparator is
in the compare mode). See the LEB description (Pin 17) for more information.
One of two complementary outputs for Channel B. QB will be at logic high if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the comparator is
in the compare mode). See the LEB description (Pin 17) for more information.
Rev. 0 | Page 7 of 16

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