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ADCMP561 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 ADCMP561은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 ADCMP561 기능
기능 (ADCMP561 / ADCMP562) Dual High Speed PECL Comparators
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ADCMP561 데이터시트, 핀배열, 회로
Dual High Speed PECL Comparators
ADCMP561/ADCMP562
FEATURES
Differential PECL compatible outputs
700 ps propagation delay input to output
75 ps propagation delay dispersion
Input common-mode range: –2.0 V to +3.0 V
Robust input protection
Differential latch control
Internal latch pull-up resistors
Power supply rejection greater than 85 dB
700 ps minimum pulse width
1.5 GHz equivalent input rise time bandwidth
Typical output rise/fall time of 500 ps
ESD protection > 4kV HBM, >200V MM
Programmable hysteresis
APPLICATIONS
Automatic test equipment
High speed instrumentation
Scope and logic analyzer front ends
Window comparators
High speed line receivers
Threshold detection
Peak detection
High speed triggers
Patient diagnostics
Disk drive read channel detection
Hand-held test instruments
Zero-crossing detectors
Line receivers and signal restoration
Clock drivers
GENERAL DESCRIPTION
The ADCMP561/ADCMP562 are high speed comparators
fabricated on Analog Devices’ proprietary XFCB process. The
devices feature a 700 ps propagation delay with less than 75 ps
overdrive dispersion. Dispersion, a measure of the difference in
propagation delay under differing overdrive conditions, is a
particularly important characteristic of comparators. A separate
programmable hysteresis pin is available on the ADCMP562.
A differential input stage permits consistent propagation delay
with a wide variety of signals in the common-mode range from
−2.0 V to +3.0 V. Outputs are complementary digital signals that
FUNCTIONAL BLOCK DIAGRAM
HYS*
NONINVERTING
INPUT
INVERTING
INPUT
ADCMP561/
ADCMP562
Q OUTPUT
Q OUTPUT
LATCH ENABLE
INPUT
LATCH ENABLE
INPUT
*ADCMP562 ONLY
Figure 1.
QA 1
16 QB
QA 2
15 QB
VDD 3
LEA 4
LEA 5
ADCMP561
TOP VIEW
(Not to Scale)
14 GND
13 LEB
12 LEB
VEE 6
–INA 7
11 VCC
10 –INB
+INA 8
9 +INB
VDD 1
20 VDD
QA 2
19 QB
QA 3
VDD 4
LEA 5
LEA 6
18 QB
ADCMP562 17 GND
TOP VIEW
(Not to Scale)
16 LEB
15 LEB
VEE 7
14 VCC
–INA 8
13 –INB
+INA 9
12 +INB
HYSA 10
11 HYSB
Figure 2. ADCMP561 16-Lead QSOP Figure 3. ADCMP562 20-Lead QSOP
are fully compatible with PECL 10 K and 10 KH logic families.
The outputs provide sufficient drive current to directly drive
transmission lines terminated in 50 Ω to VDD − 2 V. A latch
input, which is included, permits tracking, track-and-hold, or
sample-and-hold modes of operation. The latch input pins
contain internal pull-ups that set the latch in tracking mode
when left open.
The ADCMP561/ADCMP562 are specified over the industrial
temperature range (−40°C to +85°C).
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.




ADCMP561 pdf, 반도체, 판매, 대치품
ADCMP561/ADCMP562
Parameter
AC PERFORMANCE (continued)
Equivalent Input Rise Time Bandwidth1
Maximum Toggle Rate
Minimum Pulse Width
RMS Random Jitter
Unit-to-Unit Propagation Delay Skew
POWER SUPPLY
Positive Supply Current
Negative Supply Current
Logic Supply Current
Logic Supply Current
Positive Supply Voltage
Negative Supply Voltage
Logic Supply Voltage
Power Dissipation
Power Dissipation
DC Power Supply Rejection Ratio—VCC
DC Power Supply Rejection Ratio—VEE
DC Power Supply Rejection Ratio—VDD
HYSTERESIS (ADCMP562 Only)
Hysteresis
Symbol Conditions
Min
BWEQ
PWMIN
0 V to 1 V swing, 2 V/ns
>50% output swing
∆tPD < 25 ps
VOD = 400 mV, 1.3 V/ns, 312 MHz,
50% duty cycle
IVCC
IVEE
IVDD
VCC
VEE
VDD
PD
PSRRVCC
PSRRVEE
PSRRVDD
@ +5.0 V
@ −5.2 V
@ 3.3 V without load
@ 3.3 V with load
Dual
Dual
Dual
Dual, without load
Dual, with load
RHYS = 19.5 kΩ
RHYS = 8.0 kΩ
2
10
6
45
4.75
−4.96
2.5
130
180
Typ Max
1500
800
700
1.0
100
3.2 5
22 28
9 13
60 70
5.0 5.25
−5.2 −5.45
3.3 5.0
160 190
220 250
85
85
85
20
70
Unit
MHz
MHz
ps
ps
ps
mA
mA
mA
mA
V
V
V
mW
mW
dB
dB
dB
mV
mV
1 Equivalent input rise time bandwidth assumes a first-order input response and is calculated by the following formula: BWEQ = 0.22/√ (trCOMP2 – trIN2), where trIN is the
20/80 input transition time applied to the comparator and trCOMP is the effective transition time as digitized by the comparator input.
Rev. A | Page 4 of 16

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ADCMP561 전자부품, 판매, 대치품
ADCMP561/ADCMP562
Pin No.
ADCMP561 ADCMP562
14 17
15 18
16 19
20
Mnemonic
GND
QB
QB
VDD
Function
Analog Ground.
One of two complementary outputs for Channel B. QB is logic low if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the
comparator is in compare mode). See the description of PIN LEB for more information.
One of two complementary outputs for Channel B. QB is logic high if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the
comparator is in compare mode). See the description of Pin LEB for more information.
Logic Supply Terminal.
Rev. A | Page 7 of 16

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