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CN8223 데이터시트 PDF




Conexant Systems에서 제조한 전자 부품 CN8223은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 CN8223 기능
기능 ATM Transmitter/Receiver with UTOPIA Interface
제조업체 Conexant Systems
로고 Conexant Systems 로고


CN8223 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




전체 30 페이지수

미리보기를 사용할 수 없습니다

CN8223 데이터시트, 핀배열, 회로
CN8223
ATM Transmitter/Receiver with UTOPIA Interface
The CN8223 ATM Transmitter/Receiver with UTOPIA Level 1 interface provides a
single-access ATM service termination for User-to-Network (UNI) and
Network-to-Network Interfacing (NNI) in conformance with ATM Forum UNI and NNI
Specification 94/0317; Bellcore Specifications TR-TSV-000772, TR-TSV-000773,
TR-NWT-000253, and T1S1/92-185; ITU Recommendations I.432, G.707, G.751,
G.832, and Q.921; and ETSI prETS 300 213 and 300 214. Both Customer Premise
Equipment (CPE) and switching system interface functions are provided. The CN8223
provides DS1, E1, DS3, E3, E4, STS-1, and STS-3c (and STM-1) ATM cell alignment
functions. The system interface is via a parallel FIFO port or UTOPIA interface. In
addition, the CN8223 terminates the operations and maintenance flows F1, F2, and F3.
The CN8223 provides four FIFO port interfaces and one UTOPIA interface. Each
receiver port can be programmed with a particular Virtual Channel Identifier/Virtual
Path Identifier (VCI/VPI) address for message routing. VCI/VPI pages can also be
selected via masking registers.
The microprocessor can set control registers for insertion of selected header fields
by the transmitter on an individual port basis. The microprocessor can also control
insertion of all overhead and can insert errors in selected fields for test equipment
applications.
Functional Block Diagram
8
Data
Bus 8
Port
Control
UTOPIA
or FIFO
Interface
Microprocessor Microprocessor
Address
Data
Line Overhead
Cell
FIFO
8
7 8 16
4-Port
FIFO
Interface
Microprocessor
Interface
52 Control Registers
28 Status Registors
HDLC
Data
Link
8
Cell
Generation
TX
Rate
Control
8
Cell
Alignment
Header
Filter
Cell
Validation
HEC or
8 PLCP
8
Framers 1
DS3
E3 (G.751)
E3 (G.832)
STS-1
E4 (G.832)
ATM
UNI
STS-3c 1
STM-1
TAXI
8
ATM Layer
Physical Framing
Distinguishing Features
• Integrates 7 line framers with ATM
layer processing according to ATM
Forum UNI and NNI Specifications
• UTOPIA Level 1 interface
• Internal framers for DS3, E3 (G.751,
G.832), E4 (G.832), STS-1, STS-3c,
STM-1
• PLCP and G.804 HEC cell alignment
for all data rates from 1.544 Mbps to
155 Mbps
• Direct interface to TAXITM or external
T1/E1 framers
• ATM and SMDS cell modes
• 4 FIFO ports with header screening,
formatting, and transmit priority
controls
• Idle cells generated and screened
• Statistics counts latched on
one-second intervals
• Error detection and insertion
• Option insertion or generation of all
line and cell overhead
• Serial or parallel line interface
• Available evaluation module
reference design and software
• Supports Automatic Protection
Switching (APS)
Applications
• WAN equipment
• ATM switches
• Test equipment
• ATM routers and hub
Data Sheet
100046C
March 8, 2000




CN8223 pdf, 반도체, 판매, 대치품
Table of Contents
CN8223
ATM Transmitter/Receiver with UTOPIA Interface
2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.1.1 8/16-Bit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.1.2 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 Line Framers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.2.1 Internally Framed Transmit Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.2.1.1 High-Speed PECL Transmit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.2.2 Internally Framed Receive Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.2.2.1 High-Speed PECL Receive Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.2.2.2 Receiver Framing Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.2.3 Externally Framed Transmit Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.2.4 Externally Framed Receive Line Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.3 Overhead Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.3.1 Internal DS3 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.3.2 Internal G.832 E3/E4 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.3.3 Internal G.751 E3 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.3.4 STS-1 and STS-3c/STM-1 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.3.5 Transmit Framing Overhead Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.3.6 Receive Framing Overhead Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.4 Status and Alarms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.4.1 Status and Counter Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.4.2 Alarm Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2.4.3 Alarm Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2.5 Parallel Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
2.5.1 TAXI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
2.5.2 Transmit Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
2.5.3 Receive Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2.6 ATM Cell Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
2.6.1 Cell Generation for Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
2.6.1.1 CELL_GEN_x Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
2.6.1.2 Cell Generation Status and Status Interrupts for Transmit . . . . . . . . . . . . . . . 2-28
2.6.2 Cell Validation for Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
2.6.2.1 HEC Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
2.6.2.2 CELL_VAL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
2.6.2.3 Interrupts and Status Counters for Cell Validation. . . . . . . . . . . . . . . . . . . . . 2-32
2.6.3 PLCP Cell Generation for Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33
2.6.4 PLCP Cell Validation for Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35
2.6.4.1 PLCP Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35
2.6.5 PLCP Transmit/Receive Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36
iv
Conexant
100046C

4페이지










CN8223 전자부품, 판매, 대치품
CN8223
ATM Transmitter/Receiver with UTOPIA Interface
List of Figures
List of Figures
Figure 1-1.
Figure 1-2.
Figure 1-3.
Figure 1-4.
Figure 1-5.
Figure 1-6.
Figure 1-7.
Figure 1-8.
Figure 1-9.
Figure 1-10.
Figure 1-11.
Figure 1-12.
Figure 2-1.
Figure 2-2.
Figure 2-3.
Figure 2-4.
Figure 2-5.
Figure 2-6.
Figure 2-7.
Figure 2-8.
Figure 2-9.
Figure 2-10.
Figure 2-11.
Figure 2-12.
Figure 2-13.
Figure 2-14.
Figure 2-15.
Figure 2-16.
Figure 2-17.
Figure 3-1.
Figure 3-2.
Figure 3-3.
Figure 4-1.
Figure 4-2.
Figure 4-3.
Figure 4-4.
Figure 4-5.
CN8223 Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Line Framer Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
CN8223 Cell Processing Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
FIFO Port/UTOPIA Interface Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
Line Interface Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
CN8223 Connected to CAT 5 or PMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
CN8223 Connected to Bt8360 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
CN8223 Connected to Bt8510 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
CN8223 Connected to Bt8370 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
CN8223 Connected to TDK 78P7200. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
CN8223 Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
CN8223 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
CN8223 Receiver Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
CN8223 Transmitter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Internal Framer Transmitter Interface Timing with Line Encoding . . . . . . . . . . . . . . . . . . . . 2-4
Internal Framer Transmitter Interface Timing Without Line Encoding . . . . . . . . . . . . . . . . . 2-5
Internal Framer Receiver Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Timing for Internal Framer Receiver, Encoder Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
DS1 Interface Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
E1 Interface Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
DS3 Interface Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
E3 Interface Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Receiver DS1 Line Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
Transmit Framing Overhead Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Receive Framing Overhead Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
Transmit Parallel Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
Receive Parallel Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
Transmit FIFO Port Interface Timing, 53-Octet Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38
Receive FIFO Port Interface Timing, 53-Octet Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39
LINE_STATUS and OOF Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
Register Summary, Cheat Sheet 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46
Register Summary, Cheat Sheet 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47
Local Processor Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Line Interface TimingDS1, E1, DS3, E3 External Framers . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Line Interface TimingInternal Framers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
Parallel Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Overhead Port Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
100046C
Conexant
vii

7페이지


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CN8223

ATM Transmitter/Receiver with UTOPIA Interface

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