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CS18LV10245 데이터시트 PDF




CHIPLUS에서 제조한 전자 부품 CS18LV10245은 전자 산업 및 응용 분야에서
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부품번호 CS18LV10245 기능
기능 HIgh Speed Super Low Power SRAM
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CS18LV10245 데이터시트, 핀배열, 회로
High Speed Super Low Power SRAM
128K-Word By 8 Bit
CS18LV10245
„ DESCRIPTION
The CS18LV10245 is a high performance, high speed and super low power CMOS Static
Random Access Memory organized as 131,072 words by 8bits and operates from a wide range of
4.5 to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high
speed, super low power features and maximum access time of 55/70ns in 5V operation. Easy
memory expansion is provided by an active LOW chip enable (/CE) and active LOW output enable
(/OE).
The CS18LV10245 has an automatic power down feature, reducing the power consumption
significantly when chip is deselected. The CS18LV10245 is available in JEDEC standard 32-pin
sTSOP - I (8x13.4 mm), TSOP - I (8x20mm), SOP (450 mil) and PDIP (600 mil) packages.
„ FEATURES
1. Fully static operation and Tri-state output
2. TTL compatible inputs and outputs
3. Ultra low power consumption :
z 2.0V (min) data retention
z Low operation voltage : 4.5 ~ 5.5V ; 5mA1MHz (Max.) operating current (Vcc = 5.0V)
4. Standby Typ. = 0.50uA, (Typical value @ Vcc = 5.0V, TA = 25 0C)
5. Standard pin configuration
z 32 - SOP 450mil
z 32 - sTSOP-I - 8X13.4mm
z 32 - TSOP-I 8X20mm
z 32 - PDIP 600mil
„ Product Family
Part No.
Operating Temp Vcc. Range Speed (ns) Standby (Typ.) Package Type
CS18LV10245CC
32 SOP
CS18LV10245DC
CS18LV10245EC
0~70oC
0.50uA
32 STSOP
32 TSOP (I)
CS18LV10245LC
CS18LV10245CI
4.5 ~ 5.5
55/70
32 PDIP
32 SOP
CS18LV10245DI
CS18LV10245EI
-40~85oC
0.80uA
32 STSOP
32 TSOP (I)
CS18LV10245LI
32 PDIP
Note: Green package part no, sees order information.
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. .
Rev. 1.2
P1




CS18LV10245 pdf, 반도체, 판매, 대치품
High Speed Super Low Power SRAM
128K-Word By 8 Bit
CS18LV10245
„ ABSOLUTE MAXIMUM RATINGS (1)
Symbol
Parameter
Rating
Unit
VTERM
Terminal Voltage with Respect to GND
-0.5 to Vcc+0.5
V
TBIAS
Temperature Under Bias
-40 to +125
OC
TSTG
Storage Temperature
-60 to +150
OC
PT Power Dissipation
1.0 W
IOUT
DC Output Current
20 mA
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
„ OPERATING RANGE
Range
Ambient Temperature
Commercial
0~70oC
Industrial
-40~85oC
Vcc
4.5V ~5.5V
4.5V ~ 5.5V
„ CAPACITANCE (1) (TA = 25oC, f =1.0 MHz)
Symbol
Parameter
Conditions
CIN Input Capacitance
CDQ
Input/Output Capacitance
1. This parameter is guaranteed and not tested.
VIN=0V
VI/O=0V
MAX.
6
8
Unit
pF
pF
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. .
Rev. 1.2
P4

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CS18LV10245 전자부품, 판매, 대치품
High Speed Super Low Power SRAM
128K-Word By 8 Bit
CS18LV10245
„ AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 5.0V )
< READ CYCLE >
JEDEC Parameter
Description
-55 -70
Parameter Name
MIN MAX MIN MAX
Name
tAVAX
tRC Read Cycle Time
55 70
Unit
ns
tAVQV
tAA Address Access Time
55 70 ns
tELQV
tACS1 Chip Select Access Time (/CE)
55 70 ns
tELQV
tACS2 Chip Select Access Time (CE2)
55 70 ns
tGLQV
tOE Output Enable to Output Valid
20 30 ns
tE1LQX
tCLZ1 Chip Select to Output Low Z (/CE)
10
10
ns
tE2LOX
tCLZ2 Chip Select to Output Low Z (CE2)
10
10
ns
tGLQX
tOLZ Output Enable to Output in Low Z
5
5
ns
tEHQZ
tCHZ1 Chip Deselect to Output in High Z (/CE) 0 25 0 30 ns
tEHQZ
tCHZ2 Chip Deselect to Output in High Z (CE2)
0
25 0
30 ns
tGHQZ
tOHZ Output Disable to Output in High Z
0 25 0 30 ns
tAXOX
tOH Out Disable to Address Change
10 10
ns
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. .
Rev. 1.2
P7

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부품번호상세설명 및 기능제조사
CS18LV10245

HIgh Speed Super Low Power SRAM

CHIPLUS
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