Datasheet.kr   

MTV25N50E 데이터시트 PDF




Motorola Semiconductors에서 제조한 전자 부품 MTV25N50E은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 MTV25N50E 자료 제공

부품번호 MTV25N50E 기능
기능 TMOS POWER FET 25 AMPERES 500 VOLTS RDS(on) = 0.200 OHM
제조업체 Motorola Semiconductors
로고 Motorola Semiconductors 로고


MTV25N50E 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




전체 10 페이지수

미리보기를 사용할 수 없습니다

MTV25N50E 데이터시트, 핀배열, 회로
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MTV25N50E/D
Advance Information
TMOS E-FET.
Power Field Effect Transistor
D3PAK for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
The D3PAK package has the capability of housing the largest chip
size of any standard, plastic, surface mount power semiconductor.
This allows it to be used in applications that require surface mount
components with higher power and lower RDS(on) capabilities. This
high voltage MOSFET uses an advanced termination scheme to
provide enhanced voltage–blocking capability without degrading
performance over time. In addition, this advanced TMOS E–FET is
designed to withstand high energy in the avalanche and commuta-
tion modes. The new energy efficient design also offers a drain–to–
source diode with a fast recovery time. Designed for high voltage,
high speed switching applications in surface mount PWM motor
controls and both ac–dc and dc–dc power supplies. These devices
are particularly well suited for bridge circuits where diode speed and
commutating safe operating areas are critical and offer additional
safety margin against unexpected voltage transients.
D
N–Channel
G
®
Robust High Voltage Termination
Avalanche Energy Specified
S
Source–to–Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Short Heatsink Tab Manufactured – Not Sheared
Specifically Designed Leadframe for Maximum Power Dissipation
Available in 24 mm, 13–inch/500 Unit Tape & Reel, Add –RL Suffix to Part Number
MTV25N50E
TMOS POWER FET
25 AMPERES
500 VOLTS
RDS(on) = 0.200 OHM
CASE 433–01, Style 2
D3PAK Surface Mount
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Drain–to–Source Voltage
Drain–to–Gate Voltage (RGS = 1.0 M)
Gate–to–Source Voltage — Continuous
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp 10 µs)
Total Power Dissipation
Derate above 25°C
VDSS
VDGR
VGS
ID
ID
IDM
PD
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 100 Vdc, VGS = 10 Vdc, Peak IL = 25 Apk, L = 3.0 mH, RG = 25 )
TJ, Tstg
EAS
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient (1)
RθJC
RθJA
RθJA
Maximum Lead Temperature for Soldering Purposes, 1/8from case for 10 seconds
TL
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
E–FET is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Value
500
500
±20
25
15.8
88
250
2.0
– 55 to 150
938
0.5
62.5
35
260
Unit
Vdc
Vdc
Vdc
Adc
Apk
Watts
W/°C
°C
mJ
°C/W
°C
© MMoototororloa,laIncT.M19O96S Power MOSFET Transistor Device Data
1




MTV25N50E pdf, 반도체, 판매, 대치품
MTV25N50E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when cal-
culating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.
12000
11000
10000
9000
8000
7000
6000
5000
VDS = 0 V
Ciss
Crss
VGS = 0 V
TJ = 25°C
Ciss
4000
3000
2000
1000
0
–10
Crss
–5 0
5
VGS VDS
10 15
Coss
20 25
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7a. Capacitance Variation
100000
VGS = 0 V
10000
1000
100
TJ = 25°C
Ciss
Coss
Crss
10
10 100 1000
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7b. High Voltage Capacitance Variation
4 Motorola TMOS Power MOSFET Transistor Device Data

4페이지










MTV25N50E 전자부품, 판매, 대치품
MTV25N50E
INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must be
the correct size to ensure proper solder connection interface
between the board and the package. With the correct pad
geometry, the packages will self align when subjected to a
solder reflow process.
0.190
4.826
0.165
4.191
0.118
0.100 3.0
2.54
0.063
1.6
0.243
6.172
inches
mm
POWER DISSIPATION FOR A SURFACE MOUNT DEVICE
The power dissipation for a surface mount device is a
function of the drain pad size. These can vary from the
minimum pad size for soldering to a pad size given for
maximum power dissipation. Power dissipation for a surface
mount device is determined by TJ(max), the maximum rated
junction temperature of the die, RθJA, the thermal resistance
from the device junction to ambient, and the operating
temperature, TA. Using the values provided on the data sheet,
PD can be calculated as follows:
PD =
TJ(max) – TA
RθJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25°C, one can
calculate the power dissipation of the device. For a D3PAK
device, PD is calculated as follows.
PD = 150°C – 25°C = 2.0 Watts
62.5°C/W
dissipation can be increased. Although one can almost double
the power dissipation with this method, one will be giving up
area on the printed circuit board which can defeat the purpose
of using surface mount technology. For example, a graph of
RθJA versus drain pad area is shown in Figure 15.
100
Board Material = 0.0625
G–10/FR–4, 2 oz Copper
1.75 Watts
80
TA = 25°C
60
3.0 Watts
40
5.0 Watts
20
0 2 4 6 8 10
A, AREA (SQUARE INCHES)
Figure 15. Thermal Resistance versus Drain Pad
Area for the D3PAK Package (Typical)
The 62.5°C/W for the D3PAK package assumes the use of
the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 2.0 Watts. There are
other alternatives to achieving higher power dissipation from
the surface mount packages. One is to increase the area of the
drain pad. By increasing the area of the drain pad, the power
Another alternative would be to use a ceramic substrate or
an aluminum core board such as Thermal Clad. Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
Motorola TMOS Power MOSFET Transistor Device Data
7

7페이지


구       성 총 10 페이지수
다운로드[ MTV25N50E.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
MTV25N50E

TMOS POWER FET 25 AMPERES 500 VOLTS RDS(on) = 0.200 OHM

Motorola Semiconductors
Motorola Semiconductors

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵