Datasheet.kr   

MTV24C08 데이터시트 PDF




ETC에서 제조한 전자 부품 MTV24C08은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 MTV24C08 자료 제공

부품번호 MTV24C08 기능
기능 (MTV24C08 / MTV24LC08) 2-Wire 8912-Bit Serial CMOS EEPROM
제조업체 ETC
로고 ETC 로고


MTV24C08 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.



전체 14 페이지수

미리보기를 사용할 수 없습니다

MTV24C08 데이터시트, 핀배열, 회로
MYSON
TECHNOLOGY
MTV24C08/
24LC08
(Preliminary)
2-Wire 8912-Bit Serial CMOS EEPROM
FEATURES
State- of- the- Art Architecture
- Non-volatile data storage
- Standard Voltage and Low Voltage Operation
5.0(Vcc = 4.5V to 5.5V) for MTV24C08
3.0(Vcc = 2.7V to 5.5V) for 24LC08
2 wire I2C serial interface
- Provides bidirectional data transfer protocol
16-byte page write mode
- Minimizes total write time per word
Self-timed write-cycle(including auto-erase)
Durable and Reliable
- 10 years data retention after 1000K write/erase cycles
- Minimum of 1,000,000 write/erase cycles per word
- Unlimited read cycles
- ESD protection
Low standby current
GENERAL DESCRIPTION
The MTV24C08/24LC08 is a low cost, non-volatile, 4096-bit serial EEPROM with enhanced security device
and conforms to all specifications in I2C 2 wire protocol. The whole memory can be disabled (Write
Protected) by connecting the WP pin to Vcc. This section of memory then becomes unalterable unless WP
is switched to Vss. It is enhanced with security function. Every word of the memory has a programmable
security bit to permit whether it can be altered or not. The MTV24C08/24LC08's communication protocol
uses CLOCK(SCL) and DATA I/O(SDA) lines to synchronously clock data between the master (for example
a microcomputer)and the slave EEPROM devices(s) .In addition, the bus structure allows for a maximum of
16K of EEPROM memory. This supports the family in 2K, 4K, 8K, 16K devices, allowing the user to
configure the memory as the application requires with any combination of EEPROMs (not to exceed 16K).
MTV EEPROMs are designed and tested for application requiring high endurance, high reliability, and low
power consumption.
This datasheet contains new product information. Analog Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
MTV24C08/24LC08 Revision.1.0 11/03/1999
1/15




MTV24C08 pdf, 반도체, 판매, 대치품
MYSON
TECHNOLOGY
MTV24C08/
24LC08
(Preliminary)
The MTV24C08/24LC08 support a bi-directional bus oriented protocol. The protocol defines any device that
sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the
transfer is the master and the device that is controlled is the slave. The master will always initiate data
transfers and provide the clock for both transmit and receive operations. Therefore, the MTV24C08/24LC08
is considered a slave in all applications.
Clock And Data Conventions
Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. (Shown in Figures 1 and 2)
Start Condition
A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition. (Shown in Figure 2)
Stop Condition
A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition. (Shown in Figure 2)
Acknowledge
Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each
byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit.
The device that acknowledges, has to pull down the SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into account. A master must signal an end of data to the slave
by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the master to generate the STOP condition. (Shown in
Figure 3)
Devices Addressing
After generating a START condition, the bus master transmits the slave address consisting of a 4-bit device
code (1010) for the MTV24C08/24LC08, 3-bit device address (A2 A1 A0) and 1-bit value indicating the read
or write mode. All I2C EEPROMs use and internal protocol that defines a PAGE BLOCK size of 8K bits. The
MTV24C08/24LC08 contains four 2K-bits PAGE BLOCK, and the device address bits A0 and A1 are used
for determinating which PAGE BLOCK of memory segment the read/write operation will be proceeded in.
The eighth bit of slave address determines if the master device wants to read or write to the
MTV24C08/24LC08. (Refer to table B).
The MTV24C08/24LC08 monitor the bus for its corresponding slave address all the time. It generates an
acknowledge bit if the slave address was true and it is not in a programming mode.
TABLE B
Operation
Read
Write
Control Code
1010
1010
Chip Select
A2 A1 A0
A2 A1 A0
R/W
1
0
A2 are used to access device address for MTV24C08/24LC08, 8K bits’ size device.
A0 ,A1are used to access page blocks ,size of 8K bits, in the MTV24C08/24LC08
MTV24C08/24LC08 Revision.1.0 11/03/1999
4/15

4페이지










MTV24C08 전자부품, 판매, 대치품
MYSON
TECHNOLOGY
MTV24C08/
24LC08
(Preliminary)
A0
A1
A2
VSS
A0
A1
A2
VSS
18
2 24C08 7
or
3 24LC08 6
45
Dual-In-Line
package
1
2 24C08
or
3 24LC08
4
TSSOP
VCC
WP
SCL
SDA
8 VCC
7 WP
6 SCL
5 SDA
A0
A1
A2
VSS
Pin Name
A0, A1
A2
Vss
SDA
SCL
WP
Vcc
N.C.
Device Address inputs
Ground
Data I/O
Clock input
Write Protect
+ 5 V or + 3 V
18
2 24C08 7
or
3 24LC08 6
45
SO package
(M8)
VCC
WP
SCL
SDA
3.0 ABSOLUTE MAXIMUM RATINGS
Storage Temperature................................-65°C to + 125°C
Voltage with Respect to Ground.................-0.3 to + 6.5 V
NOTE: These are STRESS rating only. Appropriate conditions for operating these devices given elsewhere
may permanently damage the part. Prolonged exposure to maximum ratings may affect device reliability.
4.0 OPERATING CONDITIONS
Temperature under bias: MTV24C08/24LC08.......0°C to + 70°C
MTV24C08/24LC08-I.....-40°C to + 85°C
MTV24C08/24LC08 Revision.1.0 11/03/1999
7/15

7페이지


구       성 총 14 페이지수
다운로드[ MTV24C08.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
MTV24C08

(MTV24C08 / MTV24LC08) 2-Wire 8912-Bit Serial CMOS EEPROM

ETC
ETC

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵