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부품번호 | M8870 기능 |
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기능 | DTMF Receiver | ||
제조업체 | Clare | ||
로고 | |||
전체 9 페이지수
M-8870 DTMF Receiver
Low power consumption
· Adjustable acquisition and release times
· Central office quality and performance
· Power-down and inhibit modes (-02 only)
· Inexpensive 3.58 MHz time base
· Single 5 volt power supply
· Dial tone suppression
·· Applications include: telephone switch equipment,
remote data entry, paging systems, personal
computers, credit card systems
The M-8870 is a full DTMF Receiver that integrates both
bandsplit filter and decoder functions into a single 18-pin DIP
or SOIC package. Manufactured using CMOS process tech-
nology, the M-8870 offers low power consumption (35 mW max)
and precise data handling. Its filter section uses switched ca-
pacitor technology for both the high and low group filters and
for dial tone rejection. Its decoder uses digital counting tech-
niques to detect and decode all 16 DTMF tone pairs into a 4-
bit code. External component count is minimized by provision
of an on-chip differential input amplifier, clock generator, and
latched tri-state interface bus. Minimal external components
required include a low-cost 3.579545 MHz color burst crystal,
a timing resistor, and a timing capacitor.
Figure 1 Pin Connections
The M-8870-02 provides a “power-down” option which, when
enabled, drops consumption to less than 0.5 mW.The M-8870-
02 can also inhibit the decoding of fourth column digits (see
Table 5).
40-406-00011, Rev. F
Figure 2 Block Diagram
Page 1
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M-8870
Table 2 Absolute Maximum Ratings
Parameter
Symbol
Value
Power supply voltage (VDD - VSS)
Voltage on any pin
Current on any pin
Operating temperature
Storage temperature
VDD
VDC
IDD
TA
TS
6.0 V max
VSS -0.3, VDD +0.3
10 mA max
-40°C to + 85°C
-65°C to + 150°C
Note:
Exceeding these ratings may cause permanent damage. Functional operation under these conditions is not implied.
Parameter
Operating supply voltage
Operating supply current
Standby supply current (see Note 3)
Power consumption
Low level input voltage
High level input voltage
Input leakage current
Pullup (source) current on OE
Input impedance, signal inputs 1, 2
Steering threshold voltage
Low level output voltage
High level output voltage
Output low (sink) current
Output high (source) current
Output voltage VREF
Output resistance VREF
Table 3 DC Characteristics
Symbol
VDD
IDD
IDDQ
PO
VIL
VIH
IIH/IIL
ISO
RIN
VTSt
VOL
VOH
IOL
IOH
VREF
ROR
Min
4.75
3.5
8
2.2
VDD - 0.03
1.0
0.4
2.4
Typ*
3.0
15
0.1
6.5
10
2.5
0.8
10
Max
5.25
7.0
100
35
1.5
15.0
2.5
0.03
2.7
Units
V
mA
µA
mW
V
V
µA
µA
mΩ
V
V
V
mA
mA
V
kΩ
Test Conditions
PD=VDD
f = 3.579 MHz, VDD = 5.0 V
VIN = VSS or VDD (see Note 2)
OE = 0 V
@ 1 kHz
No load
No load
VOUT = 0.4 V
VOUT = VDD - 0.4 V
No load
Table 4 Operating Characteristics - Gain Setting Amplifier
Parameter
Symbol
Min
Typ*
Max
Units
Input leakage current
Input resistance
Input offset voltage
Power supply rejection
IN
RIN
VOS
PSRR
± 100
4
± 25
50
nA
MΩ
mV
dB
Common mode rejection
CMRR
55
dB
DC open loop voltage gain
AVOL
60
dB
Open loop unity gain bandwidth
fC
1.2 1.5
MHz
Output voltage swing
VO 3.5
VP-P
Tolerable capacitive load (GS)
CL
100 pF
Tolerable resistive load (GS)
RL
50 kΩ
Common mode range
VCM
2.5
V P-P
*Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Note:
1. All voltages referenced to VSS unless otherwise noted. For typical values VDD = 5.0 V, VSS = 0 V, TA = 25°C.
Test Conditions
VSS < VIN < VDD
1 KHz
-3.0V < VIN < 3.0V
RL ≥ 100 KΩ to VSS
No load
40-406-00011, Rev. F
Page 4
www.clare.com
4페이지 M-8870
Explanation of Events
(A) Tone bursts detected, tone duration invalid, outputs not updated.
(B) Tone #n detected, tone duration valid, tone decoded and latched in outputs.
(C) End of tone #n detected, tone absent duration valid, outputs remain latched until next valid tone.
(D) Outputs switched to high impedance state.
(E) Tone #n + 1 detected, tone duration valid, tone decoded and latched in outputs (currently high impedance).
(F) Acceptable dropout of tone #n + 1, tone absent duration invalid, outputs remain latched.
(G) End of tone #n + 1 detected, tone absent duration valid, outputs remain latched until next valid tone.
Explanation of Symbols
VIN
ESt
St/GT
Q1 - Q4
StD
OE
tREC
tREC
tID
tDO
tDP
tDA
TGTP
TGTA
DTMF composite input signal.
Early steering output. Indicates detection of valid tone frequencies.
Steering input/guard time output. Drives external RC timing circuit.
4-bit decoded tone output.
Delayed steering output. Indicates that valid frequencies have been present/absent for the required guard
time, thus constituting a valid signal.
Output enable (input). A low level shifts Q1 - Q4 to its high impedance state.
Maximum DTMF signal duration not detected as valid.
Minimum DTMF signal duration required for valid recognition.
Minimum time between valid DTMF signals.
Maximum allowable dropout during valid DTMF signal.
Time to detect the presence of valid DTMF signals.
Time to detect the absence of valid DTMF signals.
Guard time, tone present.
Guard time, tone absent.
Figure 8 Timing Diagram
40-406-00011, Rev. F
Page 7
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부품번호 | 상세설명 및 기능 | 제조사 |
M8870 | DTMF Receiver | Clare |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |