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PDF CS4392 Data sheet ( Hoja de datos )
| Número de pieza | CS4392 | |
| Descripción | 24-Bit / 192 kHz Stereo DAC with Volume Control | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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CS4392
24-Bit, 192 kHz Stereo DAC with Volume Control
Features
z Complete Stereo DAC System: Interpolation,
D/A, Output Analog Filtering
z 114 dB Dynamic Range
z 100 dB THD+N
z Up to 192kHz Sample Rates
z Direct Stream Digital Mode
z Low Clock Jitter Sensitivity
z Single +5 V Power Supply
z Selectable Digital Filters
– Fast and Slow roll-off
z Volume Control with Soft Ramp
– 1 dB Step Size
– Zero Crossing Click-Free Transitions
z Direct Interface with 5 V to 1.8 V Logic
z ATAPI Mixing Functions
z Pin Compatible with the CS4391
I
Description
The CS4392 is a complete stereo digital-to-analog sys-
tem including digital interpolation, fifth-order delta-sigma
digital-to-analog conversion, digital de-emphasis, vol-
ume control, channel mixing and analog filtering. The
advantages of this architecture include: ideal differential
linearity, no distortion mechanisms due to resistor
matching errors, no linearity drift over time and tempera-
ture, and a high tolerance to clock jitter.
The CS4392 accepts PCM data at sample rates from
4 kHz to 192 kHz, DSD audio data, has selectable digital
filters, and consumes very little power. These features
are ideal for DVD, SACD players, A/V receivers, CD and
set-top box systems. The CS4392 is pin and register
compatible with the CS4391, making easy performance
upgrades possible.
ORDERING INFORMATION
CS4392-KS
-10 to 70 °C 20-pin SOIC
CS4392-KZ
-10 to 70 °C 20-pinTSSOP
CS4392-KZZ, Lead Free -10 to 70 °C 20-pinTSSOP
CDB4392
Evaluation Board
M1 M2 M0
(SDA/CDIN) M3 (SCL/CCLK) (AD0/CS) AMUTEC BMUTEC
CMOUT FILT+
RST
SCLK
LRCK
SDATA
MODE SELECT
(CONTROL PORT)
EXTERNAL
MUTE CONTROL
REFERENCE
SERIAL
PORT
VOLUME
CONTROL
MIXER
VOLUME
CONTROL
INTERPOLATION
FILTER
INTERPOLATION
FILTER
∆Σ
DAC
∆Σ
DAC
ANALOG
FILTER
ANALOG
FILTER
AOUTA+
AOUTA-
AOUTB+
AOUTB-
Preliminary Product Information
MCLK
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2002
(All Rights Reserved)
SEP ‘04
DS459PP3
1 page  
1. PIN DESCRIPTION - PCM DATA MODE
RST
1
20
VL 2
19
SDATA
3
18
SCLK
4
17
LRCK
5
16
MCLK
6
15
M3 7
14
(SCL/CCLK) M2
8
13
(SDA/CDIN) M1
9
12
(AD0/CS) M0 10 11
AMUTEC
AOUTA-
AOUTA+
VA
AGND
AOUTB+
AOUTB-
BMUTEC
CMOUT
FILT+
CS4392
RST
1 Reset (Input) - Powers down device and resets all internal registers to their default settings.
VL 2 Logic Power (Input) - Positive power for the digital input/output.
SDATA
3 Serial Audio Data (Input) - Input for two’s complement serial audio data.
SCLK
4 Serial Clock (Input/Output) - Serial clock for the serial audio interface.
LRCK
5 Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the
serial audio data line.
MCLK
6 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
FILT+
11 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
CMOUT
12 Common Mode Voltage (Output) - Filter connection for internal quiescent voltage.
AMUTEC 20 Mute Control (Output) - The Mute Control pin goes high during power-up initialization, reset, muting,
BMUTEC 13 power-down or if the master clock to left/right clock frequency ratio is incorrect.
AOUTB-
AOUTB+
AOUTA+
AOUTA
14 Differential Analog Output (Outputs) - The full scale differential analog output level is specified in the
15 Analog Characteristics specification table.
18
19
AGND
16 Ground (Input)
VA 17 Analog Power (Input) - Positive power for the analog section.
Control Port Mode Definitions
M3 7 Mode Selection (Input) - This pins should be tied to GND level during control port mode.
SCL/CCLK
SDA/CDIN
8
9
AD0/CS
10
Serial Control Port Clock (Input) - Serial clock for the serial control port.
Serial Control Data (Input/Output) - SDA is a data I/O line in I2C mode. CDIN is the input data line for
the control port interface in SPI mode.
Address Bit 0 (I2C) / Control Port Chip Select (SPI) (Input/Output) - AD0 is a chip address pin in I2C
mode; CS is the chip select signal for SPI format.
Stand-Alone Mode Definitions
M3 7 Mode Selection (Input) - Determines the operational mode of the device.
M2 8
M1 9
M0 10
DS459PP3
5
5 Page 
CS4392
3.6 Digital Interface Format
The device will accept audio samples in several digital interface formats as illustrated in Tables 5 and 8.
The desired format is selected via the M0 and M1 pins for stand alone mode, and through the DIF2:0 bits
in the control port. For an illustration of the required relationship between the Left/Right Clock, Serial
Clock and Serial Audio Data, see Figures 4-6.
M1 M0
DESCRIPTION
0 0 Left Justified, up to 24-bit data
0 1 I2S, up to 24-bit data
1 0 Right Justified, 16-bit Data
1 1 Right Justified, 24-bit Data
FORMAT
0
1
2
3
FIGURE
4
5
6
6
Table 5. Digital Interface Format, Stand-Alone Mode Options
LRCK
SCLK
SDATA
Left Channel
Right Channel
M SB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LS B
M SB -1 -2 -3 -4 +5 +4 +3 +2 +1 LS B
Figure 4. Format 0, Left Justified up to 24-Bit Data
LRCK
SCLK
SDATA
Left Channel
Right Channel
MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB
Figure 5. Format 1, I2S up to 24-Bit Data
LRCK
SCLK
SD ATA LSB
Left Channel
Right Channel
MSB-1 -2 -3 -4 -5 -6
+6 +5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4 -5 -6
+6 +5 +4 +3 +2 +1 LSB
32 clo cks
Figure 6. Format 2, Right Justified 16-Bit Data
Format 3, Right Justified 24-Bit Data
Format 4, Right Justified 20-Bit Data. (Available in Control Port Mode only)
Format 5, Right Justified 18-Bit Data. (Available in Control Port Mode only)
DS459PP3
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CS4392.PDF ] | |
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