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PDF CS4391 Data sheet ( Hoja de datos )
| Número de pieza | CS4391 | |
| Descripción | 24-Bit / 192 kHz Stereo DAC with Volume Control | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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CS4391
24-Bit, 192 kHz Stereo DAC with Volume Control
Features
Complete Stereo DAC System: Interpolation,
D/A, Output Analog Filtering
108 dB Dynamic Range
94 dB THD+N
Direct Stream Digital Mode
Low Clock Jitter Sensitivity
+5 V to +3 V Power Supply
ATAPI Mixing
On-Chip Digital De-emphasis for 32, 44.1,
and 48 kHz
Volume Control with Soft Ramp
–119 dB Attenuation
–1 dB Step Size
–Zero Crossing Click-Free Transitions
36 mW with 3 V supply
Direct Interface with 5 V to 1.8 V Logic
I
Description
The CS4391 is a complete stereo digital-to-analog sys-
tem including digital interpolation, fourth-order delta-
sigma digital-to-analog conversion, digital de-emphasis,
volume control, channel mixing and analog filtering. The
advantages of this architecture include: ideal differential
linearity, no distortion mechanisms due to resistor
matching errors, no linearity drift over time and tempera-
ture and a high tolerance to clock jitter.
The CS4391 accepts PCM data at sample rates from
2 kHz to 192 kHz, DSD audio data, consumes very little
power and operates over a wide power supply range.
These features are ideal for DVD, A/V receivers, CD and
set-top box systems.
ORDERING INFORMATION
CS4391-KZ 20-pin TSSOP
-10 to 70 °C
CS4391-KZZ 20-pin TSSOP, Lead Free -10 to 70°C
CDB4391 Evaluation Board
M1 M2 M0
(SDA/CDIN) M3 (SCL/CCLK) (AD0/CS) AMUTEC BMUTEC
CMOUT FILT+
RST
SCLK
LRCK
SDATA
MODE SELECT
(CONTROL PORT)
EXTERNAL
MUTE CONTROL
REFERENCE
SERIAL
PORT
INTERPOLATION
FILTER
INTERPOLATOR
FILTER
VOLUME
CONTROL
MIXER
VOLUME
CONTROL
∆Σ
DAC
∆Σ
DAC
ANALOG
FILTER
ANALOG
FILTER
AOUTA+
AOUTA-
AOUTB+
AOUTB-
MCLK
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
http://www.cirrus.com
©Copyright Cirrus Logic, Inc. 2004
(All Rights Reserved)
Jul ‘04
DS335PP4
1
1 page  
CS4391
1. CHARACTERISTICS/SPECIFICATIONS
ANALOG CHARACTERISTICS (TA = 25° C; Logic "1" = VL = VA; Logic "0" = AGND; Full-Scale Out-
put Sine Wave, 997 Hz; MCLK = 12.288 MHz; SCLK = 3.072 MHz, Sample Rate = 48, 96 or 192 kHz, 24-bit data,
Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified. Test load RL = 5 kΩ, CL = 10 pF)
VA = 3 V
VA = 5 V
Parameter
Symbol Min Typ Max Min Typ Max Unit
Dynamic Performance
Dynamic Range
40 kHz Bandwidth
(Note 17)
unweighted
A-Weighted
A-Weighted
97 102 - 100 105 -
100 105 - 103 108 -
- 99 -
- 102 -
dB
dB
dB
Total Harmonic Distortion + Noise (Note 17,2) THD+N
0 dB
- -94 -89 - -94 -89 dB
-20 dB
- -82 -
- -85 - dB
-60 dB
- -42 -37 - -45 -40 dB
Idle Channel Noise / Signal-to-Noise Ratio
Interchannel Isolation
(1 kHz)
- 105 -
- 100 -
- 108 -
- 100 -
dB
dB
Power Supplies
Power Supply Current
Power Dissipation
normal operation IA + IL
power-down state IA + IL
-
-
12 TBD
30 -
-
-
normal operation
power-down
- 36 TBD -
- 0.09 -
-
17 TBD mA
60 - µA
85 TBD mW
0.3 - mW
Power Supply Rejection Ratio (1 kHz) (Note 3) PSRR - 60 -
(60 Hz)
- 40 -
- 60 - dB
- 40 - dB
Parameter
Analog Output
Full Scale Differential Output Voltage
Common Mode Voltage
Interchannel Gain Mismatch
Gain Drift
AC-Load Resistance
Load Capacitance
Symbol Min
CMOUT
RL
CL
TBD
-
-
-
5
-
Typ
1.1VA
0.5VA
0.1
100
-
-
Max
TBD
-
-
-
-
100
Units
Vpp
VDC
dB
ppm/°C
kΩ
pF
DS335PP4
5
5 Page 
CS4391
SWITCHING CHARACTERISTICS - SPI CONTROL PORT
(TA = 25° C; VL = 5.5 to 1.8 Volts; Inputs: logic 0 = AGND, logic 1 = VL, CL = 30 pF)
Parameter
Symbol
Min
SPI Mode
CCLK Clock Frequency
RST Rising Edge to CS Falling
CCLK Edge to CS Falling
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
(Note 24)
(Note 25)
(Note 26)
(Note 26)
fsclk
tsrs
tspi
tcsh
tcss
tscl
tsch
tdsu
tdh
tr2
tf2
-
500
500
1.0
20
66
66
40
15
-
-
Max
6
-
-
-
-
-
-
-
-
100
100
Unit
MHz
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
Notes: 24. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
25. Data must be held for sufficient time to bridge the transition time of CCLK.
26. For FSCK < 1 MHz
R S T t srs
CS
CCLK
C D IN
t spi t css
t scl t sch
t r2 t f2
t dsu t dh
Figure 4. SPI Control Port Timing
t csh
DS335PP4
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CS4391.PDF ] | |
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